coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _SOC_DENVERTON_NS_GPIO_H_
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#define _SOC_DENVERTON_NS_GPIO_H_
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#include <soc/gpio_defs.h>
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#define GPIO_MISCCFG 0x10
/* Miscellaneous Configuration offset */
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#define GPIO_MAX_NUM_PER_GROUP 32
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#define NUM_NC_GPI_REGS \
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(ALIGN_UP(V_PCH_GPIO_NC_PAD_MAX, GPIO_MAX_NUM_PER_GROUP) \
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/ GPIO_MAX_NUM_PER_GROUP)
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#define NUM_SC_DFX_GPI_REGS \
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(ALIGN_UP(V_PCH_GPIO_SC_DFX_PAD_MAX, GPIO_MAX_NUM_PER_GROUP) \
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/ GPIO_MAX_NUM_PER_GROUP)
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#define NUM_SC0_GPI_REGS \
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(ALIGN_UP(V_PCH_GPIO_SC0_PAD_MAX, GPIO_MAX_NUM_PER_GROUP) \
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/ GPIO_MAX_NUM_PER_GROUP)
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#define NUM_SC1_GPI_REGS \
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(ALIGN_UP(V_PCH_GPIO_SC1_PAD_MAX, GPIO_MAX_NUM_PER_GROUP) \
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/ GPIO_MAX_NUM_PER_GROUP)
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#define NUM_GPI_STATUS_REGS (NUM_NC_GPI_REGS + NUM_SC_DFX_GPI_REGS +\
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NUM_SC0_GPI_REGS + NUM_SC1_GPI_REGS)
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#define GPIO_NUM_PAD_CFG_REGS 2
/* DW0, DW1 */
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#include <
intelblocks/gpio.h
>
/* intelblocks/gpio.h depends on definitions in
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lines above and soc/gpio_defs.h */
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/*
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* DNV doesn't support dynamic GPIO PM hence GPIO community
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* MISCCFG register doesn't have PM bits
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*/
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#define MISCCFG_GPIO_PM_CONFIG_BITS 0
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#endif
/* _SOC_DENVERTON_NS_GPIO_H_ */
gpio.h
src
soc
intel
denverton_ns
include
soc
gpio.h
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