3 #include <soc/ramstage.h>
5 #include <variant/onboard.h>
13 projectid = (boardid >> 3) & 0x01;
16 params->Usb2Port0PerPortPeTxiSet = 7;
17 params->Usb2Port0PerPortTxiSet = 6;
18 params->Usb2Port0IUsbTxEmphasisEn = 3;
19 params->Usb2Port0PerPortTxPeHalf = 1;
20 params->Usb2Port1PerPortPeTxiSet = 7;
21 params->Usb2Port1PerPortTxiSet = 6;
22 params->Usb2Port1IUsbTxEmphasisEn = 3;
23 params->Usb2Port1PerPortTxPeHalf = 1;
24 params->Usb2Port2PerPortPeTxiSet = 7;
25 params->Usb2Port2PerPortTxiSet = 6;
26 params->Usb2Port2IUsbTxEmphasisEn = 3;
27 params->Usb2Port2PerPortTxPeHalf = 1;
28 params->Usb2Port3PerPortPeTxiSet = 7;
29 params->Usb2Port3PerPortTxiSet = 6;
30 params->Usb2Port3IUsbTxEmphasisEn = 3;
31 params->Usb2Port3PerPortTxPeHalf = 1;
32 params->Usb2Port4PerPortPeTxiSet = 7;
33 params->Usb2Port4PerPortTxiSet = 6;
34 params->Usb2Port4IUsbTxEmphasisEn = 3;
35 params->Usb2Port4PerPortTxPeHalf = 1;
37 params->Usb2Port0PerPortPeTxiSet = 7;
38 params->Usb2Port0PerPortTxiSet = 6;
39 params->Usb2Port0IUsbTxEmphasisEn = 3;
40 params->Usb2Port0PerPortTxPeHalf = 1;
41 params->Usb2Port1PerPortPeTxiSet = 7;
42 params->Usb2Port1PerPortTxiSet = 6;
43 params->Usb2Port1IUsbTxEmphasisEn = 3;
44 params->Usb2Port1PerPortTxPeHalf = 1;
45 params->Usb2Port2PerPortPeTxiSet = 7;
46 params->Usb2Port2PerPortTxiSet = 3;
47 params->Usb2Port2IUsbTxEmphasisEn = 2;
48 params->Usb2Port2PerPortTxPeHalf = 1;
49 params->Usb2Port3PerPortPeTxiSet = 7;
50 params->Usb2Port3PerPortTxiSet = 6;
51 params->Usb2Port3IUsbTxEmphasisEn = 3;
52 params->Usb2Port3PerPortTxPeHalf = 1;
53 params->Usb2Port4PerPortPeTxiSet = 7;
54 params->Usb2Port4PerPortTxiSet = 3;
55 params->Usb2Port4IUsbTxEmphasisEn = 2;
56 params->Usb2Port4PerPortTxPeHalf = 1;
static struct sdram_info params
uint32_t board_id(void)
board_id() - Get the board version
#define TERRA2_PROJECT_ID
void board_silicon_USB2_override(SILICON_INIT_UPD *params)