coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
w83667hg-a.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef SUPERIO_WINBOND_W83667HG_A
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#define SUPERIO_WINBOND_W83667HG_A
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/* Pinmux configuration defines */
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#define W83667HG_SPI_PINMUX_OFFSET 0x2a
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#define W83667HG_SPI_PINMUX_GPIO4_SERIAL_B_MASK (1 << 2)
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#define W83667HG_SPI_PINMUX_GPIO4 (0 << 2)
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#define W83667HG_SPI_PINMUX_SERIAL_B (1 << 2)
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/* Logical Device Numbers (LDN). */
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#define W83667HG_A_FDC 0x00
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#define W83667HG_A_PP 0x01
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#define W83667HG_A_SP1 0x02
/* Com1 */
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#define W83667HG_A_SP2 0x03
/* Com2 */
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#define W83667HG_A_KBC 0x05
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#define W83667HG_A_SPI 0x06
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#define W83667HG_A_GPIO6789_V 0x07
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#define W83667HG_A_WDT1 0x08
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#define W83667HG_A_GPIO2345_V 0x09
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#define W83667HG_A_ACPI 0x0A
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#define W83667HG_A_HWM_TSI 0x0B
/* HW monitor/SB-TSI/deep S5 */
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#define W83667HG_A_PECI 0x0C
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#define W83667HG_A_VID_BUSSEL 0x0D
/* VID and BUSSEL */
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#define W83667HG_A_GPIO_PP_OD 0x0F
/* GPIO Push-Pull/Open drain select */
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/* Virtual LDN for GPIO and SPI */
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#define W83667HG_A_SPI1 ((1 << 8) | W83667HG_A_SPI)
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#define W83667HG_A_GPIO1 ((1 << 8) | W83667HG_A_WDT1)
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#define W83667HG_A_GPIO2 ((0 << 8) | W83667HG_A_GPIO2345_V)
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#define W83667HG_A_GPIO3 ((1 << 8) | W83667HG_A_GPIO2345_V)
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#define W83667HG_A_GPIO4 ((2 << 8) | W83667HG_A_GPIO2345_V)
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#define W83667HG_A_GPIO5 ((3 << 8) | W83667HG_A_GPIO2345_V)
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#define W83667HG_A_GPIO6 ((1 << 8) | W83667HG_A_GPIO6789_V)
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#define W83667HG_A_GPIO7 ((2 << 8) | W83667HG_A_GPIO6789_V)
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#define W83667HG_A_GPIO8 ((3 << 8) | W83667HG_A_GPIO6789_V)
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#define W83667HG_A_GPIO9 ((4 << 8) | W83667HG_A_GPIO6789_V)
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#endif
/* SUPERIO_WINBOND_W83667HG_A */
src
superio
winbond
w83667hg-a
w83667hg-a.h
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