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mchbar.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SANDYBRIDGE_REGISTERS_MCHBAR_H__
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#define __SANDYBRIDGE_REGISTERS_MCHBAR_H__
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/*
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* ### IOSAV memory controller interface poking state machine notes ###
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*
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* IOSAV brings batch processing to memory training algorithms.
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*
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* The hardware is capable of executing a sequence of DRAM commands,
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* which can be composed of up to four sub-sequences.
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*
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* A sub-sequence (from now on, subseq) consists of executing the same
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* DRAM command for a configurable number of times, with adjustable
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* delay between the commands, as well as an address auto-increment
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* value, which is added after a given number of command executions.
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*
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* There are four groups of registers in MCHBAR, one for each subseq.
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* When firing up IOSAV, one needs to specify the number of subseqs it
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* should use.
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*
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* The macros for these registers can take some integer parameters.
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* Valid values are:
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* channel: 0..1 or 3 to broadcast to all channels.
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* index: 0..3
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* lane: 0..8
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*
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* These ranges are inclusive: both upper and lower bounds are valid.
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*
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*
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*
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* ### Register descriptions ###
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*
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* IOSAV_n_SP_CMD_ADDR_ch(channel, index)
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* Configures the row/column, bank and rank addresses. When a subseq
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* begins to execute, the address fields define the address of the
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* first command in the subseq. The address is updated after each
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* command as configured in the "IOSAV_n_ADDR_UPDATE" registers,
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* and the updated address is then written back into this register.
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*
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* Bitfields:
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* [15..0] Row / Column Address. Defines the ADDR pins when
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* issuing a DRAM command.
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*
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* [18..16] The number of valid row bits is this value, plus 10.
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* Note: Value 1 is not implemented.
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* Value 7 is unsupported, and thus reserved.
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*
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* [22..20] Bank select.
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* [25..24] Rank select. It is later referred to as "ranksel".
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*
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* IOSAV_n_ADDR_UPDATE_ch(channel, index)
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* How the address updates after executing a command in the subseq.
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*
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* Bitfields:
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* [0] Increment row/column address by 1.
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* [1] Increment row/column address by 8.
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* [2] Increment bank select by 1.
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* [4..3] Increment rank select by 1, 2 or 3.
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* [9..5] Known as "addr_wrap", it limits the address increments.
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* Address bits will wrap around the [addr_wrap..0] range.
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*
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* [11..10] LFSR update:
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* 00: Do not use the LFSR function.
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* 01: Undefined, treat as Reserved.
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* 10: Apply LFSR on the [addr_wrap..0] bit range.
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* 11: Apply LFSR on the [addr_wrap..3] bit range.
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*
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* [15..12] Update rate. The number of command runs between address updates. For example:
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* 0: Update every command run.
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* 1: Update every second command run. That is, half of the command rate.
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* N: Update after N command runs without updates.
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*
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* [17..16] LFSR behavior on the deselect cycles (when no subseq command is issued):
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* 0: No change w.r.t. the last issued command.
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* 1: LFSR XORs with address & command (excluding CS), but does not update.
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* 2: LFSR XORs with address & command (excluding CS), and updates.
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*
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* IOSAV_n_SP_CMD_CTRL_ch(channel, index)
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* Configures how the DRAM command lines will be driven in each
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* command of the subseq.
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*
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* Bitfields:
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* [0] !RAS signal (as driven electrically).
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* [1] !CAS signal (as driven electrically).
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* [2] !WE signal (as driven electrically).
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*
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* [4] CKE, for DIMM 0 Rank 0.
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* [5] CKE, for DIMM 0 Rank 1.
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* [6] CKE, for DIMM 1 Rank 0.
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* [7] CKE, for DIMM 1 Rank 1.
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* [11..8] ODT, per DIMM & Rank (same encoding as CKE).
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* [15..12] Chip select, per DIMM and Rank. It works as follows:
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*
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* entity CS_BLOCK is
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* port (
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* MODE : in std_logic; -- Mode select at [16]
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* RANKSEL : in std_logic_vector(0 to 3); -- Decoded "ranksel" value
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* CS_CTL : in std_logic_vector(0 to 3); -- Chip select control at [15..12]
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* CS_Q : out std_logic_vector(0 to 3) -- CS signals
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* );
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* end entity CS_BLOCK;
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*
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* architecture RTL of CS_BLOCK is
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* begin
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* if MODE = '1' then
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* CS_Q <= not RANKSEL and CS_CTL;
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* else
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* CS_Q <= CS_CTL;
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* end if;
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* end architecture RTL;
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*
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* [16] Chip Select mode control.
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* [17] Auto Precharge. Used to send RDA commands.
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*
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* IOSAV_n_SUBSEQ_CTRL_ch(channel, index)
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* The parameters of the subseq: number of repetitions of the command,
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* the delay between command executions, wait cycles after completing
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* this subseq and before the next one, and the data direction of the
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* command (read, write, neither, or both read and write).
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*
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* Bitfields:
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* [8..0] Number of repetitions of the DRAM command in this subseq.
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* [14..10] Number of DCLK cycles to wait between two successive DRAM commands.
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* [24..16] Number of DCLK cycles to idle after this subseq and before the next subseq.
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* [27..26] The direction of the data:
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* 00: None (non-data command)
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* 01: Read
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* 10: Write
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* 11: Read & Write
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*
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* IOSAV_n_ADDRESS_LFSR_ch(channel, index)
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* 23-bit LFSR state. It is written into the LFSR when the subseq is
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* loaded, and then read back from the LFSR when the subseq is done.
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*
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* Bitfields:
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* [22..0] LFSR state.
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*
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* IOSAV_SEQ_CTL_ch(channel)
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* IOSAV full sequence settings: number of subseqs, iterations, stop
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* on error, maintenance cycles...
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*
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* Bitfields:
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* [7..0] Number of full sequence executions. When this field becomes non-zero, then the
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* sequence starts running immediately. This value is decremented after completing
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* a full sequence iteration. When it is zero, the sequence is done. No decrement
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* is done if this field is set to 0xff. This is the "infinite repeat" mode, and
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* it is manually aborted by clearing this field.
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*
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* [16..8] Number of wait cycles after each sequence iteration. This wait's purpose is to
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* allow performing maintenance in infinite loops. When non-zero, RCOMP, refresh
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* and ZQXS operations can take place.
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*
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* [17] Stop-on-error mode: Whether to stop sequence execution when an error occurs.
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* [19..18] Number of subseqs. The programmed value is the index of the last valid subseq.
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* [20] If set, keep refresh disabled until the next sequence execution.
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* DANGER: Refresh must be re-enabled within the (9 * tREFI) period!
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*
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* [22] If set, sequence execution will not prevent refresh. This cannot be set when
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* bit [20] is also set, or was set on the previous sequence. This bit exists so
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* that the sequence machine can be used as a timer without affecting the memory.
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*
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* [23] If set, an output pin is asserted on the first detected error. This output can
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* be used as a trigger for an oscilloscope or a logic analyzer, which is pretty
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* useful for debugging (if you have the equipment and know where this pin is).
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*
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* IOSAV_DATA_CTL_ch(channel)
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* Data-related controls in IOSAV mode.
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*
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* Bitfields:
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* [7..0] WDB (Write Data Buffer) pattern length: [7..0] = (length / 8) - 1;
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* [15..8] WDB read pointer. Points at the data used for IOSAV write transactions.
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* [23..16] Comparison pointer. Used to compare data from IOSAV read transactions.
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* [24] If set, increment pointers only when micro-breakpoint is active.
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*
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* IOSAV_STATUS_ch(channel)
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* Provides feedback on the state of the IOSAV sequence machine.
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* Should be polled after submitting an IOSAV sequence for execution.
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*
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* Bitfields:
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* [0] IDLE: IOSAV is sleeping.
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* [1] BUSY: IOSAV is running a sequence.
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* [2] DONE: IOSAV has completed a sequence.
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* [3] ERROR: IOSAV detected an error and stopped on it, when using Stop-on-error.
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* [4] PANIC: The refresh machine issued a Panic Refresh, and IOSAV was aborted.
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* [5] RCOMP: RComp failure. Unused, consider Reserved.
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* [6] Cleared with a new sequence, and set when done and refresh counter is drained.
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*/
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/*
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* ### ECC error injection registers ###
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*
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* ECC_INJECT_COUNT_ch(channel)
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* Defines the count of write chunks (64-bit data packets) until the
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* next ECC error injection. This only seems to apply if the ECC_inject
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* field in the ECC_DFT register is 110 or 111. The count is of chunks
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* in order to allow creating ECC errors on different 64-bit chunks.
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*
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* Note that this register is only 32-bit.
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*
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* ECC_DFT_ch(channel)
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* Control ECC DFT features, such as ECC4ANA, error inject, etc.
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*
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* Bitfields:
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* [7..0] 8-bit fill value for ECC4ANA function.
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* [9..8] ECC4ANA trigger:
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* 00: ECC4ANA is off, no trigger.
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* 10: Trigger on single-bit or uncorrectable error.
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* 11: Trigger on uncorrectable error.
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*
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* [10] ECC4ANA byte select:
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* 0: Byte 0
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* 1: Byte 7
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*
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* [13..11] ECC_inject: ECC error inject options:
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* 000: No ECC error injection.
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* 100: Inject non-recoverable ECC error on GODLAT indication.
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* 101: Inject non-recoverable ECC error on ECC_INJ_ADDR_COMPARE reg match.
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* 110: Reserved.
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* 111: Inject non-recoverable ECC error on ECC error insertion counter.
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*
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* [14] ECC correction disable: when set, the MC reports every error as uncorrectable.
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* [15] Mark incoming transactions for ECC4ANA based on ECC_INJ_ADDR_COMPARE reg match.
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*
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* SCHED_SECOND_CBIT
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* More chicken bits!
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*
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* Bitfields:
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*
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* [11] Disable ECC4ANA Bug Fix. WARNING: This register is only for Ivy Bridge!
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*
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* MAD_DIMM_ch(channel)
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* Channel characteristics: number of DIMMs, number of ranks, size,
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* (enhanced) interleave options and ECC options.
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*
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* Bitfields:
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* [7..0] DIMM A size in 256 MiB units.
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* [15..8] DIMM B size in 256 MiB units.
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* [16] Select which of the DIMMs is DIMM A, should be the larger DIMM.
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* [17] DIMM A number of ranks. (0 => Single Rank, 1 => Dual Rank)
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* [18] DIMM B number of ranks.
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* [19] DIMM A DDR chip width. (0 => x8, 1 => x16)
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* [20] DIMM B DDR chip width.
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* [21] Enable Rank Interleave.
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* [22] Enable Enhanced Rank Interleave.
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* [25..24] ECC control:
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* 00: No ECC.
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* 01: ECC is active in IO, ECC logic is not active. Used with IOSAV training.
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* 10: ECC is disabled in IO, but ECC logic is enabled. Used with ECC4ANA mode.
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* 11: ECC active in both IO and ECC logic.
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*
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* ECC_INJ_ADDR_COMPARE, ECC_INJ_ADDR_MASK
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*
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* Address compare for ECC error inject. Error injection is issued when
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* ECC_INJ_ADDR_COMPARE[31..0] = ADDR[37..6] & ECC_INJ_ADDR_MASK[31..0].
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*
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* MC_LOCK
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*
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* Locking of MC registers. Each bit locks one group of registers.
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*
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* Bitfields:
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* [0] Lock all the address map registers.
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* [1] Lock all the MC configuration registers including MCIO.
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* [2] Lock all IOSAV and Init registers.
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* [3] Lock all power management registers.
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* [7] Lock all DFT features.
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*/
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/* Indexed register helper macros */
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#define Gz(r, z) ((r) + ((z) << 8))
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#define Ly(r, y) ((r) + ((y) << 2))
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#define Cx(r, x) ((r) + ((x) << 10))
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#define CxLy(r, x, y) ((r) + ((x) << 10) + ((y) << 2))
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#define GzLy(r, z, y) ((r) + ((z) << 8) + ((y) << 2))
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/* Byte lane training register base addresses */
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#define LANEBASE_B0 0x0000
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#define LANEBASE_B1 0x0200
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#define LANEBASE_B2 0x0400
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#define LANEBASE_B3 0x0600
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#define LANEBASE_ECC 0x0800
/* ECC lane is in the middle of the data lanes */
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#define LANEBASE_B4 0x1000
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#define LANEBASE_B5 0x1200
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#define LANEBASE_B6 0x1400
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#define LANEBASE_B7 0x1600
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/* Byte lane register offsets */
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#define GDCRTRAININGRESULT(ch, y) GzLy(0x0004, ch, y)
/* Test results for PI config */
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#define GDCRTRAININGRESULT1(ch) GDCRTRAININGRESULT(ch, 0)
/* 0x0004 */
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#define GDCRTRAININGRESULT2(ch) GDCRTRAININGRESULT(ch, 1)
/* 0x0008 */
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#define GDCRRX(ch, rank) GzLy(0x10, ch, rank)
/* Time setting for lane Rx */
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#define GDCRTX(ch, rank) GzLy(0x20, ch, rank)
/* Time setting for lane Tx */
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/* Register definitions */
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#define GDCRCLKRANKSUSED_ch(ch) Gz(0x0c00, ch)
/* Indicates which rank is populated */
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#define GDCRCLKCOMP_ch(ch) Gz(0x0c04, ch)
/* RCOMP result register */
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#define GDCRCKPICODE_ch(ch) Gz(0x0c14, ch)
/* PI coding for DDR CLK pins */
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#define GDCRCKLOGICDELAY_ch(ch) Gz(0x0c18, ch)
/* Logic delay of 1 QCLK in CLK slice */
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#define GDDLLFUSE_ch(ch) Gz(0x0c20, ch)
/* Used for fuse download to the DLLs */
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#define GDCRCLKDEBUGMUXCFG_ch(ch) Gz(0x0c3c, ch)
/* Debug MUX control */
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#define GDCRCMDDEBUGMUXCFG_Cz_S(ch) Gz(0x0e3c, ch)
/* Debug MUX control */
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#define CRCOMPOFST1_ch(ch) Gz(0x1810, ch)
/* DQ, CTL and CLK Offset values */
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#define GDCRTRAININGMOD_ch(ch) Gz(0x3000, ch)
/* Data training mode control */
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#define GDCRTRAININGRESULT1_ch(ch) Gz(0x3004, ch)
/* Training results according to PI */
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#define GDCRTRAININGRESULT2_ch(ch) Gz(0x3008, ch)
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#define GDCRCTLRANKSUSED_ch(ch) Gz(0x3200, ch)
/* Indicates which rank is populated */
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#define GDCRCMDCOMP_ch(ch) Gz(0x3204, ch)
/* COMP values register */
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#define GDCRCMDCTLCOMP_ch(ch) Gz(0x3208, ch)
/* COMP values register */
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#define GDCRCMDPICODING_ch(ch) Gz(0x320c, ch)
/* Command and control PI coding */
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#define GDCRTRAININGMOD 0x3400
/* Data training mode control register */
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#define GDCRDATACOMP 0x340c
/* COMP values register */
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#define CRCOMPOFST2 0x3714
/* CMD DRV, SComp and Static Leg controls */
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/*
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* The register bank that would correspond to Channel 3 are actually "broadcast" registers.
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* They can be used to write values to all channels. Use this macro instead of a literal '3'.
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*/
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#define BROADCAST_CH 3
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/* MC per-channel registers */
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#define TC_DBP_ch(ch) Cx(0x4000, ch)
/* Timings: BIN */
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#define TC_RAP_ch(ch) Cx(0x4004, ch)
/* Timings: Regular access */
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#define TC_RWP_ch(ch) Cx(0x4008, ch)
/* Timings: Read / Write */
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#define TC_OTHP_ch(ch) Cx(0x400c, ch)
/* Timings: Other parameters */
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/** WARNING: Only applies to Ivy Bridge! */
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#define TC_DTP_ch(ch) Cx(0x4014, ch)
/** Timings: Debug parameters */
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#define SCHED_SECOND_CBIT_ch(ch) Cx(0x401c, ch)
/* More chicken bits */
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#define SCHED_CBIT_ch(ch) Cx(0x4020, ch)
/* Chicken bits in scheduler */
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#define SC_ROUNDT_LAT_ch(ch) Cx(0x4024, ch)
/* Round-trip latency per rank */
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#define SC_IO_LATENCY_ch(ch) Cx(0x4028, ch)
/* IO Latency Configuration */
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#define SCRAMBLING_SEED_1_ch(ch) Cx(0x4034, ch)
/* Scrambling seed 1 */
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#define SCRAMBLING_SEED_2_LO_ch(ch) Cx(0x4038, ch)
/* Scrambling seed 2 low */
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#define SCRAMBLING_SEED_2_HI_ch(ch) Cx(0x403c, ch)
/* Scrambling seed 2 high */
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/* IOSAV Bytelane Bit-wise error */
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#define IOSAV_By_BW_SERROR_ch(ch, y) CxLy(0x4040, ch, y)
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/* IOSAV Bytelane Bit-wise compare mask */
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#define IOSAV_By_BW_MASK_ch(ch, y) CxLy(0x4080, ch, y)
349
350
/*
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* Defines the number of transactions (non-VC1 RD CAS commands) between two priority ticks.
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* Different counters for transactions that are issued on the ring agents (core or GT) and
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* transactions issued in the SA.
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*/
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#define SC_PR_CNT_CONFIG_ch(ch) Cx(0x40a8, ch)
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#define SC_PCIT_ch(ch) Cx(0x40ac, ch)
/* Page-close idle timer setup - 8 bits */
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#define PM_PDWN_CONFIG_ch(ch) Cx(0x40b0, ch)
/* Power-down (CKE-off) operation config */
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#define ECC_INJECT_COUNT_ch(ch) Cx(0x40b4, ch)
/* ECC error injection count */
359
#define ECC_DFT_ch(ch) Cx(0x40b8, ch)
/* ECC DFT features (ECC4ANA, error inject) */
360
#define SC_WR_ADD_DELAY_ch(ch) Cx(0x40d0, ch)
/* Extra WR delay to overcome WR-flyby issue */
361
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#define IOSAV_By_BW_SERROR_C_ch(ch, y) CxLy(0x4140, ch, y)
/* IOSAV Bytelane Bit-wise error */
363
364
/* IOSAV sub-sequence control registers */
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#define IOSAV_n_SP_CMD_ADDR_ch(ch, y) CxLy(0x4200, ch, y)
/* Special command address. */
366
#define IOSAV_n_ADDR_UPDATE_ch(ch, y) CxLy(0x4210, ch, y)
/* Address update control */
367
#define IOSAV_n_SP_CMD_CTRL_ch(ch, y) CxLy(0x4220, ch, y)
/* Control of command signals */
368
#define IOSAV_n_SUBSEQ_CTRL_ch(ch, y) CxLy(0x4230, ch, y)
/* Sub-sequence controls */
369
#define IOSAV_n_ADDRESS_LFSR_ch(ch, y) CxLy(0x4240, ch, y)
/* 23-bit LFSR state value */
370
371
#define PM_THML_STAT_ch(ch) Cx(0x4280, ch)
/* Thermal status of each rank */
372
#define IOSAV_SEQ_CTL_ch(ch) Cx(0x4284, ch)
/* IOSAV sequence level control */
373
#define IOSAV_DATA_CTL_ch(ch) Cx(0x4288, ch)
/* Data control in IOSAV mode */
374
#define IOSAV_STATUS_ch(ch) Cx(0x428c, ch)
/* State of the IOSAV sequence machine */
375
#define TC_ZQCAL_ch(ch) Cx(0x4290, ch)
/* ZQCAL control register */
376
#define TC_RFP_ch(ch) Cx(0x4294, ch)
/* Refresh Parameters */
377
#define TC_RFTP_ch(ch) Cx(0x4298, ch)
/* Refresh Timing Parameters */
378
#define TC_MR2_SHADOW_ch(ch) Cx(0x429c, ch)
/* MR2 shadow - copy of DDR configuration */
379
#define MC_INIT_STATE_ch(ch) Cx(0x42a0, ch)
/* IOSAV mode control */
380
#define TC_SRFTP_ch(ch) Cx(0x42a4, ch)
/* Self-refresh timing parameters */
381
#define IOSAV_ERROR_ch(ch) Cx(0x42ac, ch)
/* Data vector count of the first error */
382
#define IOSAV_DC_MASK_ch(ch) Cx(0x42b0, ch)
/* IOSAV data check masking */
383
384
#define IOSAV_By_ERROR_COUNT_ch(ch, y) CxLy(0x4340, ch, y)
/* Per-byte 16-bit error count */
385
#define IOSAV_G_ERROR_COUNT_ch(ch) Cx(0x4364, ch)
/* Global 16-bit error count */
386
387
/** WARNING: Only applies to Ivy Bridge! */
388
#define IOSAV_BYTE_SERROR_ch(ch) Cx(0x4368, ch)
/** Byte-Wise Sticky Error */
389
#define IOSAV_BYTE_SERROR_C_ch(ch) Cx(0x436c, ch)
/** Byte-Wise Sticky Error Clear */
390
391
#define PM_TRML_M_CONFIG_ch(ch) Cx(0x4380, ch)
/* Thermal mode configuration */
392
#define PM_CMD_PWR_ch(ch) Cx(0x4384, ch)
/* Power contribution of commands */
393
#define PM_BW_LIMIT_CONFIG_ch(ch) Cx(0x4388, ch)
/* Bandwidth throttling on overtemp */
394
#define SC_WDBWM_ch(ch) Cx(0x438c, ch)
/* Watermarks and starvation counter */
395
396
/* MC Channel Broadcast registers */
397
#define TC_DBP 0x4c00
/* Timings: BIN */
398
#define TC_RAP 0x4c04
/* Timings: Regular access */
399
#define TC_RWP 0x4c08
/* Timings: Read / Write */
400
#define TC_OTHP 0x4c0c
/* Timings: Other parameters */
401
402
/** WARNING: Only applies to Ivy Bridge! */
403
#define TC_DTP 0x4c14
/** Timings: Debug parameters */
404
405
#define SCHED_SECOND_CBIT 0x4c1c
/* More chicken bits */
406
#define SCHED_CBIT 0x4c20
/* Chicken bits in scheduler */
407
#define SC_ROUNDT_LAT 0x4c24
/* Round-trip latency per rank */
408
#define SC_IO_LATENCY 0x4c28
/* IO Latency Configuration */
409
#define SCRAMBLING_SEED_1 0x4c34
/* Scrambling seed 1 */
410
#define SCRAMBLING_SEED_2_LO 0x4c38
/* Scrambling seed 2 low */
411
#define SCRAMBLING_SEED_2_HI 0x4c3c
/* Scrambling seed 2 high */
412
413
#define IOSAV_By_BW_SERROR(y) Ly(0x4c40, y)
/* IOSAV Bytelane Bit-wise error */
414
#define IOSAV_By_BW_MASK(y) Ly(0x4c80, y)
/* IOSAV Bytelane Bit-wise compare mask */
415
416
/*
417
* Defines the number of transactions (non-VC1 RD CAS commands) between two priority ticks.
418
* Different counters for transactions that are issued on the ring agents (core or GT) and
419
* transactions issued in the SA.
420
*/
421
#define SC_PR_CNT_CONFIG 0x4ca8
422
#define SC_PCIT 0x4cac
/* Page-close idle timer setup - 8 bits */
423
#define PM_PDWN_CONFIG 0x4cb0
/* Power-down (CKE-off) operation config */
424
#define ECC_INJECT_COUNT 0x4cb4
/* ECC error injection count */
425
#define ECC_DFT 0x4cb8
/* ECC DFT features (ECC4ANA, error inject) */
426
#define SC_WR_ADD_DELAY 0x4cd0
/* Extra WR delay to overcome WR-flyby issue */
427
428
/** Opportunistic reads configuration during write-major-mode (WMM) */
429
#define WMM_READ_CONFIG 0x4cd4
/** WARNING: Only exists on IVB! */
430
431
#define IOSAV_By_BW_SERROR_C(y) Ly(0x4d40, y)
/* IOSAV Bytelane Bit-wise error */
432
433
#define PM_THML_STAT 0x4e80
/* Thermal status of each rank */
434
#define IOSAV_SEQ_CTL 0x4e84
/* IOSAV sequence level control */
435
#define IOSAV_DATA_CTL 0x4e88
/* Data control in IOSAV mode */
436
#define IOSAV_STATUS 0x4e8c
/* State of the IOSAV sequence machine */
437
#define TC_ZQCAL 0x4e90
/* ZQCAL control register */
438
#define TC_RFP 0x4e94
/* Refresh Parameters */
439
#define TC_RFTP 0x4e98
/* Refresh Timing Parameters */
440
#define TC_MR2_SHADOW 0x4e9c
/* MR2 shadow - copy of DDR configuration */
441
#define MC_INIT_STATE 0x4ea0
/* IOSAV mode control */
442
#define TC_SRFTP 0x4ea4
/* Self-refresh timing parameters */
443
444
/**
445
* Auxiliary register in mcmnts synthesis FUB (Functional Unit Block). Additionally, this
446
* register is also used to enable IOSAV_n_SP_CMD_ADDR optimization on Ivy Bridge.
447
*/
448
#define MCMNTS_SPARE 0x4ea8
/** WARNING: Reserved, use only on IVB! */
449
450
#define IOSAV_ERROR 0x4eac
/* Data vector count of the first error */
451
#define IOSAV_DC_MASK 0x4eb0
/* IOSAV data check masking */
452
453
#define IOSAV_By_ERROR_COUNT(y) Ly(0x4f40, y)
/* Per-byte 16-bit error counter */
454
#define IOSAV_G_ERROR_COUNT 0x4f64
/* Global 16-bit error counter */
455
456
/** WARNING: Only applies to Ivy Bridge! */
457
#define IOSAV_BYTE_SERROR 0x4f68
/** Byte-Wise Sticky Error */
458
#define IOSAV_BYTE_SERROR_C 0x4f6c
/** Byte-Wise Sticky Error Clear */
459
460
#define PM_TRML_M_CONFIG 0x4f80
/* Thermal mode configuration */
461
#define PM_CMD_PWR 0x4f84
/* Power contribution of commands */
462
#define PM_BW_LIMIT_CONFIG 0x4f88
/* Bandwidth throttling on overtemperature */
463
#define SC_WDBWM 0x4f8c
/* Watermarks and starvation counter config */
464
465
/* No, there's no need to get mad about the Memory Address Decoder */
466
#define MAD_CHNL 0x5000
/* Address Decoder Channel Configuration */
467
#define MAD_DIMM(ch) Ly(0x5004, ch)
/* Channel characteristics */
468
#define MAD_DIMM_CH0 MAD_DIMM(0)
/* Channel 0 is at 0x5004 */
469
#define MAD_DIMM_CH1 MAD_DIMM(1)
/* Channel 1 is at 0x5008 */
470
#define MAD_DIMM_CH2 MAD_DIMM(2)
/* Channel 2 is at 0x500c (unused on SNB) */
471
472
#define MAD_ZR 0x5014
/* Address Decode Zones */
473
#define MCDECS_SPARE 0x5018
/* Spare register in mcdecs synthesis FUB */
474
#define MCDECS_CBIT 0x501c
/* Chicken bits in mcdecs synthesis FUB */
475
476
#define CHANNEL_HASH 0x5024
/** WARNING: Only exists on IVB! */
477
478
#define MC_INIT_STATE_G 0x5030
/* High-level behavior in IOSAV mode */
479
#define MRC_REVISION 0x5034
/* MRC Revision */
480
#define PM_DLL_CONFIG 0x5064
/* Memory Controller I/O DLL config */
481
#define RCOMP_TIMER 0x5084
/* RCOMP evaluation timer register */
482
483
#define ECC_INJ_ADDR_COMPARE 0x5090
/* Address compare for ECC error inject */
484
#define ECC_INJ_ADDR_MASK 0x5094
/* Address mask for ECC error inject */
485
486
#define MC_LOCK 0x50fc
/* Memory Controller Lock register */
487
488
#define GFXVTBAR 0x5400
/* Base address for IGD */
489
#define VTVC0BAR 0x5410
/* Base address for PEG, USB, SATA, etc. */
490
491
/* On Ivy Bridge, this is used to enable Power Aware Interrupt Routing */
492
#define INTRDIRCTL 0x5418
/* Interrupt Redirection Control */
493
494
/* PAVP message register. Bit 0 locks PAVP settings, and bits [31..20] are an offset. */
495
#define PAVP_MSG 0x5500
496
497
#define MEM_TRML_ESTIMATION_CONFIG 0x5880
498
#define MEM_TRML_THRESHOLDS_CONFIG 0x5888
499
#define MEM_TRML_INTERRUPT 0x58a8
500
501
/* Some power MSRs are also represented in MCHBAR */
502
#define MCH_PKG_POWER_LIMIT_LO 0x59a0
/* Turbo Power Limit 1 parameters */
503
#define MCH_PKG_POWER_LIMIT_HI 0x59a4
/* Turbo Power Limit 2 parameters */
504
505
#define SSKPD 0x5d10
/* 64-bit scratchpad register */
506
#define SSKPD_HI 0x5d14
507
#define BIOS_RESET_CPL 0x5da8
/* 8-bit */
508
509
/* PCODE will sample SAPM-related registers at the end of Phase 4. */
510
#define MC_BIOS_REQ 0x5e00
/* Memory frequency request register */
511
#define MC_BIOS_DATA 0x5e04
/* Miscellaneous information for BIOS */
512
#define SAPMCTL 0x5f00
/* Bit 3 enables DDR EPG (C7i) on IVB */
513
#define M_COMP 0x5f08
/* Memory COMP control */
514
#define SAPMTIMERS 0x5f10
/* SAPM timers in 10ns (100 MHz) units */
515
516
/* WARNING: Only applies to Sandy Bridge! */
517
#define BANDTIMERS_SNB 0x5f18
/* MPLL and PPLL time to do self-banding */
518
519
/** WARNING: Only applies to Ivy Bridge! */
520
#define SAPMTIMERS2_IVB 0x5f18
/** Extra latency for DDRIO EPG exit (C7i) */
521
#define BANDTIMERS_IVB 0x5f20
/** MPLL and PPLL time to do self-banding */
522
523
/* Finalize registers. The names come from Haswell, as the finalize sequence is the same. */
524
#define HDAUDRID 0x6008
525
#define UMAGFXCTL 0x6020
526
#define VDMBDFBARKVM 0x6030
527
#define VDMBDFBARPAVP 0x6034
528
#define VTDTRKLCK 0x63fc
529
#define REQLIM 0x6800
530
#define DMIVCLIM 0x7000
531
#define PEGCTL 0x7010
/* Bit 0 is PCIPWRGAT (clock gate all PEG controllers) */
532
#define CRDTCTL3 0x740c
/* Minimum completion credits for PCIe/DMI */
533
#define CRDTCTL4 0x7410
/* Read Return Tracker credits */
534
#define CRDTLCK 0x77fc
535
536
#endif
/* __SANDYBRIDGE_REGISTERS_MCHBAR_H__ */
src
northbridge
intel
sandybridge
registers
mchbar.h
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