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amd_pci_int_defs.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef AMD_PCI_INT_DEFS_H
4 #define AMD_PCI_INT_DEFS_H
5 
6 /*
7  * PIRQ and device routing - these define the index
8  * into the FCH PCI_INTR 0xC00/0xC01 interrupt
9  * routing table
10  */
11 #if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON)
12 #define FCH_INT_TABLE_SIZE 0x54
13 #elif CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
14 #define FCH_INT_TABLE_SIZE 0x42
15 #endif
16 
17 #define PIRQ_NC 0x1F /* Not Used */
18 #define PIRQ_A 0x00 /* INT A */
19 #define PIRQ_B 0x01 /* INT B */
20 #define PIRQ_C 0x02 /* INT C */
21 #define PIRQ_D 0x03 /* INT D */
22 #define PIRQ_E 0x04 /* INT E */
23 #define PIRQ_F 0x05 /* INT F */
24 #define PIRQ_G 0x06 /* INT G */
25 #define PIRQ_H 0x07 /* INT H */
26 #define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings - See FCH Spec */
27 #define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */
28 #define PIRQ_MISC1 0x0A /* Miscellaneous1 IRQ Settings */
29 #define PIRQ_MISC2 0x0B /* Miscellaneous2 IRQ Settings */
30 #define PIRQ_SIRQA 0x0C /* Serial IRQ INTA */
31 #define PIRQ_SIRQB 0x0D /* Serial IRQ INTB */
32 #define PIRQ_SIRQC 0x0E /* Serial IRQ INTC */
33 #define PIRQ_SIRQD 0x0F /* Serial IRQ INTD */
34 #define PIRQ_SCI 0x10 /* SCI IRQ */
35 #define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */
36 #define PIRQ_ASF 0x12 /* ASF */
37 #define PIRQ_HDA 0x13 /* HDA 14h.2 */
38 #define PIRQ_FC 0x14 /* FC */
39 #define PIRQ_GEC 0x15 /* GEC */
40 #define PIRQ_PMON 0x16 /* Performance Monitor */
41 #if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
42 #define PIRQ_SD 0x17 /* SD */
43 #endif
44 #define PIRQ_IMC0 0x20 /* IMC INT0 */
45 #define PIRQ_IMC1 0x21 /* IMC INT1 */
46 #define PIRQ_IMC2 0x22 /* IMC INT2 */
47 #define PIRQ_IMC3 0x23 /* IMC INT3 */
48 #define PIRQ_IMC4 0x24 /* IMC INT4 */
49 #define PIRQ_IMC5 0x25 /* IMC INT5 */
50 #define PIRQ_OHCI1 0x30 /* USB OHCI 12h.0 */
51 #define PIRQ_EHCI1 0x31 /* USB EHCI 12h.2 */
52 #define PIRQ_OHCI2 0x32 /* USB OHCI 13h.0 */
53 #define PIRQ_EHCI2 0x33 /* USB EHCI 13h.2 */
54 #define PIRQ_OHCI3 0x34 /* USB OHCI 16h.0 */
55 #define PIRQ_EHCI3 0x35 /* USB EHCI 16h.2 */
56 #define PIRQ_OHCI4 0x36 /* USB OHCI 14h.5 */
57 #define PIRQ_IDE 0x40 /* IDE 14h.1 */
58 #define PIRQ_SATA 0x41 /* SATA 11h.0 */
59 #if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON)
60 #define PIRQ_SD 0x42 /* SD 14h.7 */
61 #define PIRQ_GPP0 0x50 /* GPP INT 0 */
62 #define PIRQ_GPP1 0x51 /* GPP INT 1 */
63 #define PIRQ_GPP2 0x52 /* GPP INT 2 */
64 #define PIRQ_GPP3 0x53 /* GPP INT 3 */
65 #endif
66 
67 #endif /* AMD_PCI_INT_DEFS_H */