coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
usb.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef _SOC_USB_H_
4 #define _SOC_USB_H_
5 
6 #include <stdint.h>
7 
8 /* Per Port HS Transmitter Emphasis */
9 #define USB2_EMP_OFF 0
10 #define USB2_DE_EMP_ON 1
11 #define USB2_PRE_EMP_ON 2
12 #define USB2_DE_EMP_ON_PRE_EMP_ON 3
13 
14 /* Per Port Half Bit Pre-emphasis */
15 #define USB2_FULL_BIT_PRE_EMP 0
16 #define USB2_HALF_BIT_PRE_EMP 1
17 
18 /* Per Port HS Preemphasis Bias */
19 #define USB2_BIAS_0MV 0
20 #define USB2_BIAS_11P25MV 1
21 #define USB2_BIAS_16P9MV 2
22 #define USB2_BIAS_28P15MV 3
23 #define USB2_BIAS_39P35MV 5
24 #define USB2_BIAS_45MV 6
25 #define USB2_BIAS_56P3MV 7
26 
27 struct usb2_port_config {
29  uint8_t ocpin;
34 };
35 
36 /* USB Overcurrent pins definition */
37 enum {
38  OC0 = 0,
39  OC1,
40  OC2,
41  OC3,
42  OC4,
43  OC5,
44  OC6,
45  OC7,
47  OC_SKIP = 0xff, /* Skip OC programming */
48 };
49 
50 /* Standard USB Port based on length:
51  * - External
52  * - Back Panel
53  * - OTG
54  * - M.2
55  * - Internal device down */
56 
57 #define USB2_PORT_EMPTY { \
58  .enable = 0, \
59  .ocpin = OC_SKIP, \
60  .tx_bias = USB2_BIAS_0MV, \
61  .tx_emp_enable = USB2_EMP_OFF, \
62  .pre_emp_bias = USB2_BIAS_0MV, \
63  .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
64 }
65 
66 /* Length = 11.5"-12" */
67 #define USB2_PORT_LONG(pin) { \
68  .enable = 1, \
69  .ocpin = (pin), \
70  .tx_bias = USB2_BIAS_39P35MV, \
71  .tx_emp_enable = USB2_PRE_EMP_ON, \
72  .pre_emp_bias = USB2_BIAS_56P3MV, \
73  .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
74 }
75 
76 /* Length = 6"-11.49" */
77 #define USB2_PORT_MID(pin) { \
78  .enable = 1, \
79  .ocpin = (pin), \
80  .tx_bias = USB2_BIAS_0MV, \
81  .tx_emp_enable = USB2_PRE_EMP_ON, \
82  .pre_emp_bias = USB2_BIAS_56P3MV, \
83  .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
84 }
85 
86 /* Length = 3"-5.99" */
87 #define USB2_PORT_SHORT(pin) { \
88  .enable = 1, \
89  .ocpin = (pin), \
90  .tx_bias = USB2_BIAS_39P35MV, \
91  .tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \
92  .pre_emp_bias = USB2_BIAS_39P35MV, \
93  .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \
94 }
95 
96 /* Max TX and Pre-emp settings */
97 #define USB2_PORT_MAX(pin) { \
98  .enable = 1, \
99  .ocpin = (pin), \
100  .tx_bias = USB2_BIAS_56P3MV, \
101  .tx_emp_enable = USB2_PRE_EMP_ON, \
102  .pre_emp_bias = USB2_BIAS_56P3MV, \
103  .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
104 }
105 
106 /* Type-C Port, no BC1.2 charge detect module / MUX
107  * Length = 3.0" - 9.00" */
108 #define USB2_PORT_TYPE_C(pin) { \
109  .enable = 1, \
110  .ocpin = (pin), \
111  .tx_bias = USB2_BIAS_0MV, \
112  .tx_emp_enable = USB2_PRE_EMP_ON, \
113  .pre_emp_bias = USB2_BIAS_56P3MV, \
114  .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
115 }
116 
117 struct usb3_port_config {
118  uint8_t enable;
119  uint8_t ocpin;
122 };
123 
124 #define USB3_PORT_EMPTY { \
125  .enable = 0, \
126  .ocpin = OC_SKIP, \
127  .tx_de_emp = 0x00, \
128  .tx_downscale_amp = 0x00, \
129 }
130 
131 #define USB3_PORT_DEFAULT(pin) { \
132  .enable = 1, \
133  .ocpin = (pin), \
134  .tx_de_emp = 0x0, \
135  .tx_downscale_amp = 0x00, \
136 }
137 
138 #endif
@ OC2
Definition: usb.h:41
@ OC7
Definition: usb.h:46
@ OC3
Definition: usb.h:42
@ OC5
Definition: usb.h:44
@ OCMAX
Definition: usb.h:47
@ OC0
Definition: usb.h:39
@ OC_SKIP
Definition: usb.h:48
@ OC1
Definition: usb.h:40
@ OC6
Definition: usb.h:45
@ OC4
Definition: usb.h:43
unsigned char uint8_t
Definition: stdint.h:8
uint8_t tx_bias
Definition: usb.h:30
uint8_t ocpin
Definition: usb.h:29
uint8_t pre_emp_bias
Definition: usb.h:32
uint8_t enable
Definition: usb.h:28
uint8_t pre_emp_bit
Definition: usb.h:33
uint8_t tx_emp_enable
Definition: usb.h:31
uint8_t ocpin
Definition: usb.h:132
uint8_t tx_downscale_amp
Definition: usb.h:134
uint8_t tx_de_emp
Definition: usb.h:133
uint8_t enable
Definition: usb.h:131