coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
psp_verstage_addr.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef AMD_PICASSO_PSP_VERSTAGE_ADDR_H
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#define AMD_PICASSO_PSP_VERSTAGE_ADDR_H
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/*
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* Start of available space is 0x15000 and this is where the
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* header for the user app (verstage) must be mapped.
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* Size is 0x28000 bytes
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*/
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#define PSP_SRAM_START 0x15000
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#define PSP_SRAM_SIZE (160K)
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#define VERSTAGE_START PSP_SRAM_START
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/*
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* The temp stack can be made much smaller if needed - even 256 bytes
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* should be sufficient. This is just for the function mapping the
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* actual stack.
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*/
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#define PSP_VERSTAGE_TEMP_STACK_START 0x32000
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#define PSP_VERSTAGE_TEMP_STACK_SIZE (4K)
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/*
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* The top of the stack must be 4k aligned, so set the bottom as 4k aligned
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* and make the size a multiple of 4k
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*/
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#define PSP_VERSTAGE_STACK_START 0x33000
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#define PSP_VERSTAGE_STACK_SIZE (40K)
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#endif
/* AMD_PICASSO_PSP_VERSTAGE_ADDR_H */
src
soc
amd
picasso
include
soc
psp_verstage_addr.h
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