coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio_defs_pch_h.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef _SOC_TIGERLAKE_GPIO_DEFS_PCH_H_H_
4 #define _SOC_TIGERLAKE_GPIO_DEFS_PCH_H_H_
5 
6 #ifndef __ACPI__
7 #include <stddef.h>
8 #endif
10 
11 #define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */
12 
13 #define NUM_GPIO_COMx_GPI_REGS(n) \
14  (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
15 
16 #define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS)
17 #define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS)
18 #define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS)
19 #define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS)
20 #define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS)
21 #define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS)
22 
23 #define NUM_GPI_STATUS_REGS \
24  ((NUM_GPIO_COM0_GPI_REGS) +\
25  (NUM_GPIO_COM1_GPI_REGS) +\
26  (NUM_GPIO_COM2_GPI_REGS) +\
27  (NUM_GPIO_COM3_GPI_REGS) +\
28  (NUM_GPIO_COM4_GPI_REGS) +\
29  (NUM_GPIO_COM5_GPI_REGS))
30 /*
31  * IOxAPIC IRQs for the GPIOs
32  */
33 
34 /* Group A */
35 #define GPP_A0_IRQ 0x18
36 #define GPP_A1_IRQ 0x19
37 #define GPP_A2_IRQ 0x1A
38 #define GPP_A3_IRQ 0x1B
39 #define GPP_A4_IRQ 0x1C
40 #define GPP_A5_IRQ 0x1D
41 #define GPP_A6_IRQ 0x1E
42 #define GPP_A7_IRQ 0x1F
43 #define GPP_A8_IRQ 0x20
44 #define GPP_A9_IRQ 0x21
45 #define GPP_A10_IRQ 0x22
46 #define GPP_A11_IRQ 0x23
47 #define GPP_A12_IRQ 0x24
48 #define GPP_A13_IRQ 0x25
49 #define GPP_A14_IRQ 0x26
50 #define GPP_A15_IRQ 0x27
51 #define GPP_A16_IRQ 0x28
52 #define GPP_A17_IRQ 0x29
53 #define GPP_A18_IRQ 0x2A
54 #define GPP_A19_IRQ 0x2B
55 #define GPP_A20_IRQ 0x2C
56 #define GPP_A21_IRQ 0x2D
57 #define GPP_A22_IRQ 0x2E
58 #define GPP_A23_IRQ 0x2F
59 
60 /* Group R */
61 #define GPP_R0_IRQ 0x37
62 #define GPP_R1_IRQ 0x38
63 #define GPP_R2_IRQ 0x39
64 #define GPP_R3_IRQ 0x3A
65 #define GPP_R4_IRQ 0x3B
66 #define GPP_R5_IRQ 0x3C
67 #define GPP_R6_IRQ 0x3D
68 #define GPP_R7_IRQ 0x3E
69 
70 /* Group B */
71 #define GPP_B0_IRQ 0x30
72 #define GPP_B1_IRQ 0x31
73 #define GPP_B2_IRQ 0x32
74 #define GPP_B3_IRQ 0x33
75 #define GPP_B4_IRQ 0x34
76 #define GPP_B5_IRQ 0x35
77 #define GPP_B6_IRQ 0x36
78 #define GPP_B7_IRQ 0x37
79 #define GPP_B8_IRQ 0x38
80 #define GPP_B9_IRQ 0x39
81 #define GPP_B10_IRQ 0x3A
82 #define GPP_B11_IRQ 0x3B
83 #define GPP_B12_IRQ 0x3C
84 #define GPP_B13_IRQ 0x3D
85 #define GPP_B14_IRQ 0x3E
86 #define GPP_B15_IRQ 0x3F
87 #define GPP_B16_IRQ 0x40
88 #define GPP_B17_IRQ 0x41
89 #define GPP_B18_IRQ 0x42
90 #define GPP_B19_IRQ 0x43
91 #define GPP_B20_IRQ 0x44
92 #define GPP_B21_IRQ 0x45
93 #define GPP_B22_IRQ 0x46
94 #define GPP_B23_IRQ 0x47
95 
96 /* Group C */
97 #define GPP_C0_IRQ 0x48
98 #define GPP_C1_IRQ 0x49
99 #define GPP_C2_IRQ 0x4A
100 #define GPP_C3_IRQ 0x4B
101 #define GPP_C4_IRQ 0x4C
102 #define GPP_C5_IRQ 0x4D
103 #define GPP_C6_IRQ 0x4E
104 #define GPP_C7_IRQ 0x4F
105 #define GPP_C8_IRQ 0x50
106 #define GPP_C9_IRQ 0x51
107 #define GPP_C10_IRQ 0x52
108 #define GPP_C11_IRQ 0x53
109 #define GPP_C12_IRQ 0x54
110 #define GPP_C13_IRQ 0x55
111 #define GPP_C14_IRQ 0x56
112 #define GPP_C15_IRQ 0x57
113 #define GPP_C16_IRQ 0x58
114 #define GPP_C17_IRQ 0x59
115 #define GPP_C18_IRQ 0x5A
116 #define GPP_C19_IRQ 0x5B
117 #define GPP_C20_IRQ 0x5C
118 #define GPP_C21_IRQ 0x5D
119 #define GPP_C22_IRQ 0x5E
120 #define GPP_C23_IRQ 0x5F
121 
122 /* Group D */
123 #define GPP_D0_IRQ 0x60
124 #define GPP_D1_IRQ 0x61
125 #define GPP_D2_IRQ 0x62
126 #define GPP_D3_IRQ 0x63
127 #define GPP_D4_IRQ 0x64
128 #define GPP_D5_IRQ 0x65
129 #define GPP_D6_IRQ 0x66
130 #define GPP_D7_IRQ 0x67
131 #define GPP_D8_IRQ 0x68
132 #define GPP_D9_IRQ 0x69
133 #define GPP_D10_IRQ 0x6A
134 #define GPP_D11_IRQ 0x6B
135 #define GPP_D12_IRQ 0x6C
136 #define GPP_D13_IRQ 0x6D
137 #define GPP_D14_IRQ 0x6E
138 #define GPP_D15_IRQ 0x6F
139 #define GPP_D16_IRQ 0x70
140 #define GPP_D17_IRQ 0x71
141 #define GPP_D18_IRQ 0x72
142 #define GPP_D19_IRQ 0x73
143 #define GPP_D20_IRQ 0x74
144 #define GPP_D21_IRQ 0x75
145 #define GPP_D22_IRQ 0x76
146 #define GPP_D23_IRQ 0x77
147 
148 /* Group S */
149 #define GPP_S0_IRQ 0x3F
150 #define GPP_S1_IRQ 0x40
151 #define GPP_S2_IRQ 0x41
152 #define GPP_S3_IRQ 0x42
153 #define GPP_S4_IRQ 0x43
154 #define GPP_S5_IRQ 0x44
155 #define GPP_S6_IRQ 0x45
156 #define GPP_S7_IRQ 0x46
157 
158 /* Group G */
159 #define GPP_G0_IRQ 0x18
160 #define GPP_G1_IRQ 0x19
161 #define GPP_G2_IRQ 0x1A
162 #define GPP_G3_IRQ 0x1B
163 #define GPP_G4_IRQ 0x1C
164 #define GPP_G5_IRQ 0x1D
165 #define GPP_G6_IRQ 0x1E
166 #define GPP_G7_IRQ 0x1F
167 #define GPP_G8_IRQ 0x20
168 #define GPP_G9_IRQ 0x21
169 #define GPP_G10_IRQ 0x22
170 #define GPP_G11_IRQ 0x23
171 #define GPP_G12_IRQ 0x24
172 #define GPP_G13_IRQ 0x25
173 #define GPP_G14_IRQ 0x26
174 #define GPP_G15_IRQ 0x27
175 
176 /* Group VGPIO */
177 #define VGPIO4_IRQ 0x28
178 
179 /* Group GPD */
180 #define GPD0_IRQ 0x29
181 #define GPD1_IRQ 0x2A
182 #define GPD2_IRQ 0x2B
183 #define GPD3_IRQ 0x2C
184 #define GPD4_IRQ 0x2D
185 #define GPD5_IRQ 0x2E
186 #define GPD6_IRQ 0x2F
187 #define GPD7_IRQ 0x30
188 #define GPD8_IRQ 0x31
189 #define GPD9_IRQ 0x32
190 #define GPD10_IRQ 0x33
191 #define GPD11_IRQ 0x34
192 #define GPD12_IRQ 0x35
193 
194 /* Group E */
195 #define GPP_E0_IRQ 0x35
196 #define GPP_E1_IRQ 0x36
197 #define GPP_E2_IRQ 0x37
198 #define GPP_E3_IRQ 0x38
199 #define GPP_E4_IRQ 0x39
200 #define GPP_E5_IRQ 0x3A
201 #define GPP_E6_IRQ 0x3B
202 #define GPP_E7_IRQ 0x3C
203 #define GPP_E8_IRQ 0x3D
204 #define GPP_E9_IRQ 0x3E
205 #define GPP_E10_IRQ 0x3F
206 #define GPP_E11_IRQ 0x40
207 #define GPP_E12_IRQ 0x41
208 
209 /* Group F */
210 #define GPP_F0_IRQ 0x42
211 #define GPP_F1_IRQ 0x43
212 #define GPP_F2_IRQ 0x44
213 #define GPP_F3_IRQ 0x45
214 #define GPP_F4_IRQ 0x46
215 #define GPP_F5_IRQ 0x47
216 #define GPP_F6_IRQ 0x48
217 #define GPP_F7_IRQ 0x49
218 #define GPP_F8_IRQ 0x4A
219 #define GPP_F9_IRQ 0x4B
220 #define GPP_F10_IRQ 0x4C
221 #define GPP_F11_IRQ 0x4D
222 #define GPP_F12_IRQ 0x4E
223 #define GPP_F13_IRQ 0x4F
224 #define GPP_F14_IRQ 0x50
225 #define GPP_F15_IRQ 0x51
226 #define GPP_F16_IRQ 0x52
227 #define GPP_F17_IRQ 0x53
228 #define GPP_F18_IRQ 0x54
229 #define GPP_F19_IRQ 0x55
230 #define GPP_F20_IRQ 0x56
231 #define GPP_F21_IRQ 0x57
232 #define GPP_F22_IRQ 0x58
233 #define GPP_F23_IRQ 0x59
234 
235 /* Group H */
236 #define GPP_H0_IRQ 0x5A
237 #define GPP_H1_IRQ 0x5B
238 #define GPP_H2_IRQ 0x5C
239 #define GPP_H3_IRQ 0x5D
240 #define GPP_H4_IRQ 0x5E
241 #define GPP_H5_IRQ 0x5F
242 #define GPP_H6_IRQ 0x60
243 #define GPP_H7_IRQ 0x61
244 #define GPP_H8_IRQ 0x62
245 #define GPP_H9_IRQ 0x63
246 #define GPP_H10_IRQ 0x64
247 #define GPP_H11_IRQ 0x65
248 #define GPP_H12_IRQ 0x66
249 #define GPP_H13_IRQ 0x67
250 #define GPP_H14_IRQ 0x68
251 #define GPP_H15_IRQ 0x69
252 #define GPP_H16_IRQ 0x6A
253 #define GPP_H17_IRQ 0x6B
254 #define GPP_H18_IRQ 0x6C
255 #define GPP_H19_IRQ 0x6D
256 #define GPP_H20_IRQ 0x6E
257 #define GPP_H21_IRQ 0x6F
258 #define GPP_H22_IRQ 0x70
259 #define GPP_H23_IRQ 0x71
260 
261 /* Group K */
262 #define GPP_K0_IRQ 0x72
263 #define GPP_K1_IRQ 0x73
264 #define GPP_K2_IRQ 0x74
265 #define GPP_K3_IRQ 0x75
266 #define GPP_K4_IRQ 0x76
267 #define GPP_K5_IRQ 0x77
268 #define GPP_K6_IRQ 0x18
269 #define GPP_K7_IRQ 0x19
270 #define GPP_K8_IRQ 0x1A
271 #define GPP_K9_IRQ 0x1B
272 #define GPP_K10_IRQ 0x1C
273 #define GPP_K11_IRQ 0x1D
274 
275 /* Group J */
276 #define GPP_J0_IRQ 0x1E
277 #define GPP_J1_IRQ 0x1F
278 #define GPP_J2_IRQ 0x20
279 #define GPP_J3_IRQ 0x21
280 #define GPP_J4_IRQ 0x22
281 #define GPP_J5_IRQ 0x23
282 #define GPP_J6_IRQ 0x24
283 #define GPP_J7_IRQ 0x25
284 #define GPP_J8_IRQ 0x26
285 #define GPP_J9_IRQ 0x27
286 
287 /* Group I */
288 #define GPP_I0_IRQ 0x28
289 #define GPP_I1_IRQ 0x29
290 #define GPP_I2_IRQ 0x2A
291 #define GPP_I3_IRQ 0x2B
292 #define GPP_I4_IRQ 0x2C
293 #define GPP_I5_IRQ 0x2D
294 #define GPP_I6_IRQ 0x2E
295 #define GPP_I7_IRQ 0x2F
296 #define GPP_I8_IRQ 0x30
297 #define GPP_I9_IRQ 0x31
298 #define GPP_I10_IRQ 0x32
299 #define GPP_I11_IRQ 0x33
300 #define GPP_I12_IRQ 0x34
301 #define GPP_I13_IRQ 0x35
302 #define GPP_I14_IRQ 0x36
303 
304 /* Register defines. */
305 #define GPIO_MISCCFG 0x10
306 #define GPE_DW_SHIFT 8
307 #define GPE_DW_MASK 0xfff00
308 #define HOSTSW_OWN_REG_0 0xc0
309 #define GPI_INT_STS_0 0x100
310 #define GPI_INT_EN_0 0x120
311 #define GPI_SMI_STS_0 0x180
312 #define GPI_SMI_EN_0 0x1A0
313 #define GPI_NMI_STS_0 0x1c0
314 #define GPI_NMI_EN_0 0x1e0
315 #define PAD_CFG_BASE 0x600
316 
317 #endif