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gpio_defs.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #ifndef _SOC_BLOCK_GPIO_DEFS_H_
4 #define _SOC_BLOCK_GPIO_DEFS_H_
5 
6 #include <intelblocks/gpio.h>
7 
8 #define PAD_CFG0_TX_STATE_BIT 0
9 #define PAD_CFG0_TX_STATE (1 << PAD_CFG0_TX_STATE_BIT)
10 #define PAD_CFG0_RX_STATE_BIT 1
11 #define PAD_CFG0_RX_STATE (1 << PAD_CFG0_RX_STATE_BIT)
12 #define PAD_CFG0_TX_DISABLE (1 << 8)
13 #define PAD_CFG0_RX_DISABLE (1 << 9)
14 #define PAD_CFG0_MODE_SHIFT 10
15 #define PAD_CFG0_MODE_MASK (7 << 10)
16 #define PAD_CFG0_MODE_GPIO (0 << 10)
17 #define PAD_CFG0_MODE_FUNC(x) ((x) << 10)
18 #define PAD_CFG0_MODE_NF1 (1 << 10)
19 #define PAD_CFG0_MODE_NF2 (2 << 10)
20 #define PAD_CFG0_MODE_NF3 (3 << 10)
21 #define PAD_CFG0_MODE_NF4 (4 << 10)
22 #define PAD_CFG0_MODE_NF5 (5 << 10)
23 #define PAD_CFG0_MODE_NF6 (6 << 10)
24 #define PAD_CFG0_MODE_NF7 (7 << 10)
25 #define PAD_CFG0_ROUTE_MASK (0xF << 17)
26 #define PAD_CFG0_ROUTE_NMI (1 << 17)
27 #define PAD_CFG0_ROUTE_SMI (1 << 18)
28 #define PAD_CFG0_ROUTE_SCI (1 << 19)
29 #define PAD_CFG0_ROUTE_IOAPIC (1 << 20)
30 #define PAD_CFG0_RXTENCFG_MASK (3 << 21)
31 #define PAD_CFG0_RXINV_MASK (1 << 23)
32 #define PAD_CFG0_RX_POL_INVERT (1 << 23)
33 #define PAD_CFG0_RX_POL_NONE (0 << 23)
34 #define PAD_CFG0_PREGFRXSEL (1 << 24)
35 #define PAD_CFG0_TRIG_MASK (3 << 25)
36 #define PAD_CFG0_TRIG_LEVEL (0 << 25)
37 #define PAD_CFG0_TRIG_EDGE_SINGLE (1 << 25) /* controlled by RX_INVERT*/
38 #define PAD_CFG0_TRIG_OFF (2 << 25)
39 #define PAD_CFG0_TRIG_EDGE_BOTH (3 << 25)
40 #define PAD_CFG0_NAFVWE_ENABLE (1 << 27)
41 #define PAD_CFG0_RXRAW1_MASK (1 << 28)
42 #define PAD_CFG0_RXPADSTSEL_MASK (1 << 29)
43 #define PAD_CFG0_RESET_MASK (3 << 30)
44 #define PAD_CFG0_LOGICAL_RESET_PWROK (0U << 30)
45 #define PAD_CFG0_LOGICAL_RESET_DEEP (1U << 30)
46 #define PAD_CFG0_LOGICAL_RESET_PLTRST (2U << 30)
47 #define PAD_CFG0_LOGICAL_RESET_RSMRST (3U << 30)
48 
49 /*
50  * Use the fourth bit in IntSel field to indicate gpio
51  * ownership. This field is RO and hence not used during
52  * gpio configuration.
53  */
54 #define PAD_CFG_OWN_GPIO_DRIVER (1 << 4)
55 #define PAD_CFG_OWN_GPIO_ACPI (0 << 4)
56 #define PAD_CFG_OWN_GPIO(own) PAD_CFG_OWN_GPIO_##own
57 
58 #define PAD_CFG1_IRQ_MASK (0xff << 0)
59 #define PAD_CFG1_IOSTERM_MASK (0x3 << 8)
60 #define PAD_CFG1_IOSTERM_SAME (0x0 << 8)
61 #define PAD_CFG1_IOSTERM_DISPUPD (0x1 << 8)
62 #define PAD_CFG1_IOSTERM_ENPD (0x2 << 8)
63 #define PAD_CFG1_IOSTERM_ENPU (0x3 << 8)
64 #define PAD_CFG1_PULL_MASK (0xf << 10)
65 #define PAD_CFG1_PULL_NONE (0x0 << 10)
66 #define PAD_CFG1_PULL_DN_5K (0x2 << 10)
67 #define PAD_CFG1_PULL_DN_20K (0x4 << 10)
68 #define PAD_CFG1_PULL_UP_1K (0x9 << 10)
69 #define PAD_CFG1_PULL_UP_5K (0xa << 10)
70 #define PAD_CFG1_PULL_UP_2K (0xb << 10)
71 #define PAD_CFG1_PULL_UP_20K (0xc << 10)
72 #define PAD_CFG1_PULL_UP_667 (0xd << 10)
73 #define PAD_CFG1_PULL_NATIVE (0xf << 10)
74 #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY)
75 /* Tx enabled driving last value driven, Rx enabled */
76 #define PAD_CFG1_IOSSTATE_TxLASTRxE (0x0 << 14)
77 /* Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller
78  * internally */
79 #define PAD_CFG1_IOSSTATE_Tx0RxDCRx0 (0x1 << 14)
80 /* Tx enabled driving 0, Rx disabled and Rx driving 1 back to its controller
81  * internally */
82 #define PAD_CFG1_IOSSTATE_Tx0RxDCRx1 (0x2 << 14)
83 /* Tx enabled driving 1, Rx disabled and Rx driving 0 back to its controller
84  * internally */
85 #define PAD_CFG1_IOSSTATE_Tx1RxDCRx0 (0x3 << 14)
86 /* Tx enabled driving 1, Rx disabled and Rx driving 1 back to its controller
87  * internally */
88 #define PAD_CFG1_IOSSTATE_Tx1RxDCRx1 (0x4 << 14)
89 /* Tx enabled driving 0, Rx enabled */
90 #define PAD_CFG1_IOSSTATE_Tx0RxE (0x5 << 14)
91 /* Tx enabled driving 1, Rx enabled */
92 #define PAD_CFG1_IOSSTATE_Tx1RxE (0x6 << 14)
93 /* Hi-Z, Rx driving 0 back to its controller internally */
94 #define PAD_CFG1_IOSSTATE_HIZCRx0 (0x7 << 14)
95 /* Hi-Z, Rx driving 1 back to its controller internally */
96 #define PAD_CFG1_IOSSTATE_HIZCRx1 (0x8 << 14)
97 #define PAD_CFG1_IOSSTATE_TxDRxE (0x9 << 14) /* Tx disabled, Rx enabled */
98 #define PAD_CFG1_IOSSTATE_IGNORE (0xf << 14) /* Ignore Iostandby */
99 #define PAD_CFG1_IOSSTATE_MASK (0xf << 14) /* mask to extract Iostandby bits */
100 #define PAD_CFG1_IOSSTATE_SHIFT 14 /* set Iostandby bits [17:14] */
101 #else /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY */
102 #define PAD_CFG1_IOSSTATE_MASK 0
103 #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY */
104 
105 #define PAD_CFG2_DEBEN 1
106 /* Debounce Duration = (2 ^ PAD_CFG2_DEBOUNCE_x_RTC) * RTC clock duration */
107 #define PAD_CFG2_DEBOUNCE_8_RTC (0x3 << 1)
108 #define PAD_CFG2_DEBOUNCE_16_RTC (0x4 << 1)
109 #define PAD_CFG2_DEBOUNCE_32_RTC (0x5 << 1)
110 #define PAD_CFG2_DEBOUNCE_64_RTC (0x6 << 1)
111 #define PAD_CFG2_DEBOUNCE_128_RTC (0x7 << 1)
112 #define PAD_CFG2_DEBOUNCE_256_RTC (0x8 << 1)
113 #define PAD_CFG2_DEBOUNCE_512_RTC (0x9 << 1)
114 #define PAD_CFG2_DEBOUNCE_1K_RTC (0xa << 1)
115 #define PAD_CFG2_DEBOUNCE_2K_RTC (0xb << 1)
116 #define PAD_CFG2_DEBOUNCE_4K_RTC (0xc << 1)
117 #define PAD_CFG2_DEBOUNCE_8K_RTC (0xd << 1)
118 #define PAD_CFG2_DEBOUNCE_16K_RTC (0xe << 1)
119 #define PAD_CFG2_DEBOUNCE_32K_RTC (0xf << 1)
120 #define PAD_CFG2_DEBOUNCE_MASK 0x1f
121 
122 /* voltage tolerance 0=3.3V default 1=1.8V tolerant */
123 #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL)
124 #define PAD_CFG1_TOL_MASK (0x1 << 25)
125 #define PAD_CFG1_TOL_1V8 (0x1 << 25)
126 #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL */
127 
128 #define PAD_FUNC(value) PAD_CFG0_MODE_##value
129 #define PAD_RESET(value) PAD_CFG0_LOGICAL_RESET_##value
130 #define PAD_RX_POL(value) PAD_CFG0_RX_POL_##value
131 #define PAD_IRQ_ROUTE(value) PAD_CFG0_ROUTE_##value
132 #define PAD_TRIG(value) PAD_CFG0_TRIG_##value
133 #define PAD_PULL(value) PAD_CFG1_PULL_##value
134 #define PAD_LOCK(value) GPIO_##value
135 
136 /* Disable the input/output buffer of the pad */
137 #define PAD_CFG0_BUF_NO_DISABLE (0)
138 #define PAD_CFG0_BUF_TX_DISABLE PAD_CFG0_TX_DISABLE
139 #define PAD_CFG0_BUF_RX_DISABLE PAD_CFG0_RX_DISABLE
140 #define PAD_CFG0_BUF_TX_RX_DISABLE \
141  (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE)
142 
143 #define PAD_BUF(value) PAD_CFG0_BUF_##value
144 
145 #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY)
146 #define PAD_IOSSTATE(value) PAD_CFG1_IOSSTATE_##value
147 #define PAD_IOSTERM(value) PAD_CFG1_IOSTERM_##value
148 #else
149 #define PAD_IOSSTATE(value) 0
150 #define PAD_IOSTERM(value) 0
151 #endif
152 
153 #define PAD_IRQ_CFG(route, trig, inv) \
154  (PAD_IRQ_ROUTE(route) | \
155  PAD_TRIG(trig) | \
156  PAD_RX_POL(inv))
157 
158 #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT)
159 #define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv) \
160  (PAD_IRQ_ROUTE(route1) | \
161  PAD_IRQ_ROUTE(route2) | \
162  PAD_TRIG(trig) | \
163  PAD_RX_POL(inv))
164 #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT */
165 
166 #define _PAD_CFG_STRUCT(__pad, __config0, __config1) \
167  { \
168  .pad = __pad, \
169  .pad_config[0] = __config0, \
170  .pad_config[1] = __config1, \
171  .lock_action = PAD_LOCK(UNLOCK), \
172  }
173 
174 #define _PAD_CFG_STRUCT_LOCK(__pad, __config0, __config1, __action) \
175  { \
176  .pad = __pad, \
177  .pad_config[0] = __config0, \
178  .pad_config[1] = __config1, \
179  .lock_action = __action, \
180  }
181 
182 #if GPIO_NUM_PAD_CFG_REGS > 2
183 #define _PAD_CFG_STRUCT_3(__pad, __config0, __config1, __config2) \
184  { \
185  .pad = __pad, \
186  .pad_config[0] = __config0, \
187  .pad_config[1] = __config1, \
188  .pad_config[2] = __config2, \
189  .lock_action = PAD_LOCK(UNLOCK), \
190  }
191 #else
192 #define _PAD_CFG_STRUCT_3(__pad, __config0, __config1, __config2) \
193  _PAD_CFG_STRUCT(__pad, __config0, __config1)
194 #endif
195 
196 /* Native function configuration */
197 #define PAD_CFG_NF(pad, pull, rst, func) \
198  _PAD_CFG_STRUCT(pad, \
199  PAD_RESET(rst) | PAD_FUNC(func), \
200  PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE))
201 
202 /* Native function configuration with lock */
203 #define PAD_CFG_NF_LOCK(pad, pull, func, lock_action) \
204  _PAD_CFG_STRUCT_LOCK(pad, \
205  PAD_RESET(PWROK) | PAD_FUNC(func), \
206  PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE), \
207  PAD_LOCK(lock_action))
208 
209 #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL)
210 /* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S
211  Not applicable to all SOCs. Refer EDS
212  */
213 #define PAD_CFG_NF_1V8(pad, pull, rst, func) \
214  _PAD_CFG_STRUCT(pad, \
215  PAD_RESET(rst) | PAD_FUNC(func), \
216  PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_TOL_1V8)
217 #endif
218 
219 /* Native function configuration for standby state */
220 #define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \
221  _PAD_CFG_STRUCT(pad, \
222  PAD_RESET(rst) | PAD_FUNC(func), \
223  PAD_PULL(pull) | PAD_IOSSTATE(iosstate))
224 
225 /* Native function configuration for standby state, also configuring
226  iostandby as masked */
227 #define PAD_CFG_NF_IOSTANDBY_IGNORE(pad, pull, rst, func) \
228  _PAD_CFG_STRUCT(pad, \
229  PAD_RESET(rst) | PAD_FUNC(func), \
230  PAD_PULL(pull) | PAD_IOSSTATE(IGNORE))
231 
232 /* Native function configuration for standby state, also configuring
233  iosstate and iosterm */
234 #define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \
235  _PAD_CFG_STRUCT(pad, \
236  PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
237  PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
238 
239 /* Native function configuration with "native function virtual wire
240  messaging enable (NAFVWE_ENABLE)" */
241 #define PAD_CFG_NF_VWEN(pad, pull, rst, func) \
242  _PAD_CFG_STRUCT(pad, \
243  PAD_RESET(rst) | PAD_FUNC(func) | PAD_CFG0_NAFVWE_ENABLE,\
244  PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE))
245 
246 /* General purpose output, no pullup/down. */
247 #define PAD_CFG_GPO(pad, val, rst) \
248  _PAD_CFG_STRUCT(pad, \
249  PAD_FUNC(GPIO) | PAD_RESET(rst) | \
250  PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \
251  PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE))
252 
253 /* General purpose output with lock, no pullup/down. */
254 #define PAD_CFG_GPO_LOCK(pad, val, lock_action) \
255  _PAD_CFG_STRUCT_LOCK(pad, \
256  PAD_FUNC(GPIO) | PAD_RESET(PWROK) | \
257  PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \
258  PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE), \
259  PAD_LOCK(lock_action))
260 
261 /* General purpose output, with termination specified */
262 #define PAD_CFG_TERM_GPO(pad, val, pull, rst) \
263  _PAD_CFG_STRUCT(pad, \
264  PAD_FUNC(GPIO) | PAD_RESET(rst) | \
265  PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \
266  PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE))
267 
268 /* General purpose output, no pullup/down. */
269 #define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \
270  _PAD_CFG_STRUCT(pad, \
271  PAD_FUNC(GPIO) | PAD_RESET(rst) | \
272  PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \
273  PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | \
274  PAD_CFG_OWN_GPIO(DRIVER))
275 
276 /* General purpose output. */
277 #define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \
278  _PAD_CFG_STRUCT(pad, \
279  PAD_FUNC(GPIO) | PAD_RESET(rst) | \
280  PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \
281  PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm))
282 
283 /* General purpose input */
284 #define PAD_CFG_GPI(pad, pull, rst) \
285  _PAD_CFG_STRUCT(pad, \
286  PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE), \
287  PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE))
288 
289 /* General purpose input with lock */
290 #define PAD_CFG_GPI_LOCK(pad, pull, lock_action) \
291  _PAD_CFG_STRUCT_LOCK(pad, \
292  PAD_FUNC(GPIO) | PAD_RESET(PWROK) | PAD_BUF(TX_DISABLE), \
293  PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE), \
294  PAD_LOCK(lock_action))
295 
296 #define PAD_CFG_GPI_TRIG_IOSSTATE_OWN(pad, pull, rst, trig, iosstate, own) \
297  _PAD_CFG_STRUCT(pad, \
298  PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | PAD_BUF(TX_DISABLE), \
299  PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own) | PAD_IOSSTATE(iosstate))
300 
301 #define PAD_CFG_GPI_TRIG_IOS_OWN(pad, pull, rst, trig, iosstate, iosterm, own) \
302  _PAD_CFG_STRUCT(pad, \
303  PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | PAD_BUF(TX_DISABLE), \
304  PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own) | \
305  PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
306 
307 /*
308  * General purpose input. The following macro sets the
309  * Host Software Pad Ownership to GPIO Driver mode.
310  */
311 #define PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own) \
312  _PAD_CFG_STRUCT(pad, \
313  PAD_FUNC(GPIO) | PAD_RESET(rst) | \
314  PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE), \
315  PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own))
316 
317 #define PAD_CFG_GPI_TRIG_OWN_LOCK(pad, pull, rst, trig, own, lock_action) \
318  _PAD_CFG_STRUCT_LOCK(pad, \
319  PAD_FUNC(GPIO) | PAD_RESET(rst) | \
320  PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE), \
321  PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own), PAD_LOCK(lock_action))
322 
323 #define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \
324  _PAD_CFG_STRUCT(pad, \
325  PAD_FUNC(GPIO) | PAD_RESET(rst) | \
326  PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), \
327  PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | PAD_IOSSTATE(TxDRxE))
328 
329 #define PAD_CFG_GPI_GPIO_DRIVER_LOCK(pad, pull, lock_action) \
330  _PAD_CFG_STRUCT_LOCK(pad, \
331  PAD_FUNC(GPIO) | PAD_RESET(PWROK) | \
332  PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), \
333  PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | PAD_IOSSTATE(TxDRxE), \
334  PAD_LOCK(lock_action))
335 
336 #define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \
337  _PAD_CFG_STRUCT(pad, \
338  PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_RX_DISABLE), \
339  PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | \
340  PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
341 
342 #define PAD_CFG_GPIO_HI_Z(pad, pull, rst, iosstate, iosterm) \
343  _PAD_CFG_STRUCT(pad, \
344  PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_RX_DISABLE), \
345  PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
346 
347 /* GPIO Interrupt */
348 #define PAD_CFG_GPI_INT(pad, pull, rst, trig) \
349  PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, DRIVER)
350 
351 /* GPIO Interrupt with lock */
352 #define PAD_CFG_GPI_INT_LOCK(pad, pull, trig, lock_action) \
353  PAD_CFG_GPI_TRIG_OWN_LOCK(pad, pull, PWROK, trig, DRIVER, lock_action)
354 
355 /*
356  * No Connect configuration for unconnected or unused pad.
357  * Both TX and RX are disabled. RX disabling is done to avoid unnecessary
358  * setting of GPI_STS and to prevent triggering the internal logic by floating
359  * pads.
360  */
361 #define PAD_NC(pad, pull) \
362  _PAD_CFG_STRUCT(pad, \
363  PAD_FUNC(GPIO) | PAD_RESET(DEEP) | \
364  PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), \
365  PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE))
366 
367 /* No Connect configuration with lock */
368 #define PAD_NC_LOCK(pad, pull, lock_action) \
369  _PAD_CFG_STRUCT_LOCK(pad, \
370  PAD_RESET(PWROK) | PAD_FUNC(GPIO) | \
371  PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), \
372  PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE), \
373  PAD_LOCK(lock_action))
374 
375 /* General purpose input, routed to APIC */
376 #define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \
377  _PAD_CFG_STRUCT(pad, \
378  PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \
379  PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \
380  PAD_IOSSTATE(TxDRxE))
381 
382 /* General purpose input with lock, routed to APIC */
383 #define PAD_CFG_GPI_APIC_LOCK(pad, pull, trig, inv, lock_action) \
384  _PAD_CFG_STRUCT_LOCK(pad, \
385  PAD_FUNC(GPIO) | PAD_RESET(PWROK) | PAD_BUF(TX_DISABLE) | \
386  PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \
387  PAD_IOSSTATE(TxDRxE), \
388  PAD_LOCK(lock_action))
389 
390 /* General purpose input, routed to APIC - with IOStandby Config*/
391 #define PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \
392  _PAD_CFG_STRUCT(pad, \
393  PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \
394  PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \
395  PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
396 
397 /*
398  * The following APIC macros assume the APIC will handle the filtering
399  * on its own end. One just needs to pass an active high message into the
400  * ITSS.
401  */
402 #define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \
403  PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, INVERT)
404 
405 #define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \
406  PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE)
407 
408 #define PAD_CFG_GPI_APIC_EDGE_LOW(pad, pull, rst) \
409  PAD_CFG_GPI_APIC(pad, pull, rst, EDGE_SINGLE, INVERT)
410 
411 /* General purpose input, routed to SMI */
412 #define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \
413  _PAD_CFG_STRUCT(pad, \
414  PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \
415  PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \
416  PAD_IOSSTATE(TxDRxE))
417 
418 /* General purpose input, routed to SMI */
419 #define PAD_CFG_GPI_SMI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \
420  _PAD_CFG_STRUCT(pad, \
421  PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \
422  PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \
423  PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
424 
425 #define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \
426  PAD_CFG_GPI_SMI(pad, pull, rst, trig, INVERT)
427 
428 #define PAD_CFG_GPI_SMI_HIGH(pad, pull, rst, trig) \
429  PAD_CFG_GPI_SMI(pad, pull, rst, trig, NONE)
430 
431 /* General purpose input, routed to SCI */
432 #define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \
433  _PAD_CFG_STRUCT(pad, \
434  PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \
435  PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \
436  PAD_IOSSTATE(TxDRxE))
437 
438 /* General purpose input with lock, routed to SCI */
439 #define PAD_CFG_GPI_SCI_LOCK(pad, pull, trig, inv, lock_action) \
440  _PAD_CFG_STRUCT_LOCK(pad, \
441  PAD_FUNC(GPIO) | PAD_RESET(PWROK) | PAD_BUF(TX_DISABLE) | \
442  PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \
443  PAD_IOSSTATE(TxDRxE), PAD_LOCK(lock_action))
444 
445 /* General purpose input, routed to SCI */
446 #define PAD_CFG_GPI_SCI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \
447  _PAD_CFG_STRUCT(pad, \
448  PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \
449  PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \
450  PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
451 
452 #define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \
453  PAD_CFG_GPI_SCI(pad, pull, rst, trig, INVERT)
454 
455 #define PAD_CFG_GPI_SCI_LOW_LOCK(pad, pull, trig, lock_action) \
456  PAD_CFG_GPI_SCI_LOCK(pad, pull, trig, INVERT, lock_action)
457 
458 #define PAD_CFG_GPI_SCI_HIGH(pad, pull, rst, trig) \
459  PAD_CFG_GPI_SCI(pad, pull, rst, trig, NONE)
460 
461 #define PAD_CFG_GPI_SCI_HIGH_LOCK(pad, pull, trig, lock_action) \
462  PAD_CFG_GPI_SCI_LOCK(pad, pull, trig, NONE, lock_action)
463 
464 #define PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, inv, dur) \
465  _PAD_CFG_STRUCT_3(pad, \
466  PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \
467  PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \
468  PAD_IOSSTATE(TxDRxE), PAD_CFG2_DEBEN | PAD_CFG2_##dur)
469 
470 #define PAD_CFG_GPI_SCI_LOW_DEBEN(pad, pull, rst, trig, dur) \
471  PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, INVERT, dur)
472 
473 #define PAD_CFG_GPI_SCI_HIGH_DEBEN(pad, pull, rst, trig, dur) \
474  PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, NONE, dur)
475 
476 /* General purpose input, routed to NMI */
477 #define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \
478  _PAD_CFG_STRUCT(pad, \
479  PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \
480  PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \
481  PAD_IOSSTATE(TxDRxE))
482 
483 #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT)
484 #define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \
485  _PAD_CFG_STRUCT(pad, \
486  PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \
487  PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \
488  PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE))
489 
490 #define PAD_CFG_GPI_DUAL_ROUTE_LOCK(pad, pull, rst, trig, inv, route1, route2, lock_action) \
491  _PAD_CFG_STRUCT_LOCK(pad, \
492  PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \
493  PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \
494  PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE), \
495  PAD_LOCK(lock_action))
496 
497 #define PAD_CFG_GPI_IRQ_WAKE(pad, pull, rst, trig, inv) \
498  PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, IOAPIC, SCI)
499 
500 #define PAD_CFG_GPI_IRQ_WAKE_LOCK(pad, pull, trig, inv, lock_action) \
501  PAD_CFG_GPI_DUAL_ROUTE_LOCK(pad, pull, PWROK, trig, inv, IOAPIC, SCI, lock_action)
502 
503 #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT */
504 
505 #endif /* _SOC_BLOCK_GPIO_DEFS_H_ */