coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
board.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef _COREBOOT_SRC_MAINBOARD_GOOGLE_HEROBRINE_BOARD_H_
4 #define _COREBOOT_SRC_MAINBOARD_GOOGLE_HEROBRINE_BOARD_H_
5 
6 #include <assert.h>
7 #include <gpio.h>
8 
9 
10 #if CONFIG(BOARD_GOOGLE_HEROBRINE_REV0)
11 #define GPIO_EC_IN_RW GPIO(68)
12 #define GPIO_AP_EC_INT GPIO(142)
13 #define GPIO_H1_AP_INT GPIO(54)
14 #elif CONFIG(BOARD_GOOGLE_SENOR)
15 #define GPIO_EC_IN_RW dead_code_t(gpio_t)
16 #define GPIO_AP_EC_INT dead_code_t(gpio_t)
17 #define GPIO_H1_AP_INT dead_code_t(gpio_t)
18 #else
19 #define GPIO_EC_IN_RW GPIO(156)
20 #define GPIO_AP_EC_INT GPIO(18)
21 #define GPIO_H1_AP_INT GPIO(104)
22 #endif
23 
24 #define GPIO_SD_CD_L GPIO(91)
25 
26 #if CONFIG(BOARD_GOOGLE_HEROBRINE_REV0)
27 #define USB_HUB_LDO_EN GPIO(24)
28 #else
29 /* For Herobrine board and all variants */
30 #define USB_HUB_LDO_EN GPIO(157)
31 #endif
32 
33 #define GPIO_AMP_ENABLE GPIO(63)
34 #define GPIO_MI2S1_SCK GPIO(106)
35 #define GPIO_MI2S1_DATA0 GPIO(107)
36 #define GPIO_MI2S1_WS GPIO(108)
37 
38 #define QCOM_SC7280_SKU1 0x0
39 #define QCOM_SC7280_SKU2 0x1
40 
41 /* Fingerprint-specific GPIOs. Only for fingerprint-enabled devices. */
42 #if CONFIG(HEROBRINE_HAS_FINGERPRINT)
43 #define GPIO_FPMCU_BOOT0 (CONFIG(BOARD_GOOGLE_HEROBRINE_REV0) ? GPIO(77) : GPIO(68))
44 #define GPIO_FP_RST_L GPIO(78)
45 #define GPIO_EN_FP_RAILS (CONFIG(BOARD_GOOGLE_HEROBRINE_REV0) ? GPIO(42) : GPIO(77))
46 #else
47 #define GPIO_FPMCU_BOOT0 dead_code_t(gpio_t)
48 #define GPIO_FP_RST_L dead_code_t(gpio_t)
49 #define GPIO_EN_FP_RAILS dead_code_t(gpio_t)
50 #endif
51 
52 void setup_chromeos_gpios(void);
53 
54 #endif /* _COREBOOT_SRC_MAINBOARD_GOOGLE_HEROBRINE_BOARD_H_ */
void setup_chromeos_gpios(void)
Definition: chromeos.c:10