coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
iomap.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef AMD_STONEYRIDGE_IOMAP_H
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#define AMD_STONEYRIDGE_IOMAP_H
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/* MMIO Ranges */
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#define PSP_MAILBOX_BAR3_BASE 0xf0a00000
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#define SPI_BASE_ADDRESS 0xfec10000
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#define IO_APIC2_ADDR 0xfec20000
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#define ALINK_AHB_ADDRESS 0xfedc0000
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/* I2C fixed address */
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#define APU_I2C0_BASE 0xfedc2000
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#define APU_I2C1_BASE 0xfedc3000
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#define APU_I2C2_BASE 0xfedc4000
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#define APU_I2C3_BASE 0xfedc5000
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#define APU_UART0_BASE 0xfedc6000
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#define APU_UART1_BASE 0xfedc8000
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#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1)
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/* I/O Ranges */
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#define ACPI_IO_BASE 0x400
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#define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00)
/* 4 bytes */
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#define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00)
/* 2 bytes */
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#define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02)
/* 2 bytes */
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#define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04)
/* 2 bytes */
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#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x08)
/* 6 bytes */
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#define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x10)
/* 8 bytes */
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#define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00)
/* 4 bytes */
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#define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04)
/* 4 bytes */
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#define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x18)
/* 4 bytes */
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#define SMB_BASE_ADDR 0xb00
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#define PM2_INDEX 0xcd0
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#define PM2_DATA 0xcd1
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#define BIOSRAM_INDEX 0xcd4
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#define BIOSRAM_DATA 0xcd5
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#define AB_INDX 0xcd8
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#define AB_DATA (AB_INDX+4)
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#endif
/* AMD_STONEYRIDGE_IOMAP_H */
src
soc
amd
stoneyridge
include
soc
iomap.h
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