coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
iomap.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef AMD_STONEYRIDGE_IOMAP_H
4 #define AMD_STONEYRIDGE_IOMAP_H
5 
6 /* MMIO Ranges */
7 #define PSP_MAILBOX_BAR3_BASE 0xf0a00000
8 #define SPI_BASE_ADDRESS 0xfec10000
9 #define IO_APIC2_ADDR 0xfec20000
10 
11 #define ALINK_AHB_ADDRESS 0xfedc0000
12 
13 /* I2C fixed address */
14 #define APU_I2C0_BASE 0xfedc2000
15 #define APU_I2C1_BASE 0xfedc3000
16 #define APU_I2C2_BASE 0xfedc4000
17 #define APU_I2C3_BASE 0xfedc5000
18 
19 #define APU_UART0_BASE 0xfedc6000
20 #define APU_UART1_BASE 0xfedc8000
21 
22 #define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1)
23 
24 /* I/O Ranges */
25 #define ACPI_IO_BASE 0x400
26 #define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) /* 4 bytes */
27 #define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) /* 2 bytes */
28 #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */
29 #define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) /* 2 bytes */
30 #define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x08) /* 6 bytes */
31 #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x10) /* 8 bytes */
32 #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */
33 #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */
34 #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x18) /* 4 bytes */
35 #define SMB_BASE_ADDR 0xb00
36 #define PM2_INDEX 0xcd0
37 #define PM2_DATA 0xcd1
38 #define BIOSRAM_INDEX 0xcd4
39 #define BIOSRAM_DATA 0xcd5
40 #define AB_INDX 0xcd8
41 #define AB_DATA (AB_INDX+4)
42 
43 #endif /* AMD_STONEYRIDGE_IOMAP_H */