coreboot
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gpio_soc_defs.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _SOC_CANNONLAKE_GPIO_SOC_DEFS_H_
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#define _SOC_CANNONLAKE_GPIO_SOC_DEFS_H_
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/*
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* Most of the fixed numbers and macros are based on the GPP groups.
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* The GPIO groups are accessed through register blocks called
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* communities.
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*/
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#define GPP_A 0x0
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#define GPP_B 0x1
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#define GPP_G 0x2
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#define GROUP_SPI 0x3
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#define GPP_D 0x5
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#define GPP_F 0x6
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#define GPP_H 0x7
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#define GROUP_VGPIO0 0x8
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#define GROUP_VGPIO1 0x9
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#define GPD 0xA
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#define GROUP_AZA 0xB
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#define GROUP_CPU 0xC
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#define GPP_C 0x4
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#define GPP_E 0xD
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#define GROUP_JTAG 0xE
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#define GROUP_HVMOS 0xF
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#define GPIO_MAX_NUM_PER_GROUP 24
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/*
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* GPIOs are ordered monotonically increasing to match ACPI/OS driver.
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*/
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/* Group A */
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#define GPP_A0 0
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#define GPP_A1 1
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#define GPP_A2 2
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#define GPP_A3 3
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#define GPP_A4 4
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#define GPP_A5 5
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#define GPP_A6 6
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#define GPP_A7 7
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#define GPP_A8 8
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#define GPP_A9 9
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#define GPP_A10 10
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#define GPP_A11 11
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#define GPP_A12 12
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#define GPP_A13 13
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#define GPP_A14 14
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#define GPP_A15 15
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#define GPP_A16 16
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#define GPP_A17 17
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#define GPP_A18 18
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#define GPP_A19 19
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#define GPP_A20 20
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#define GPP_A21 21
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#define GPP_A22 22
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#define GPP_A23 23
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#define ESPI_CLK_LOOPBK 24
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/* Group B */
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#define GPP_B0 25
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#define GPP_B1 26
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#define GPP_B2 27
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#define GPP_B3 28
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#define GPP_B4 29
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#define GPP_B5 30
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#define GPP_B6 31
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#define GPP_B7 32
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#define GPP_B8 33
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#define GPP_B9 34
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#define GPP_B10 35
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#define GPP_B11 36
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#define GPP_B12 37
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#define GPP_B13 38
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#define GPP_B14 39
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#define GPP_B15 40
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#define GPP_B16 41
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#define GPP_B17 42
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#define GPP_B18 43
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#define GPP_B19 44
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#define GPP_B20 45
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#define GPP_B21 46
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#define GPP_B22 47
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#define GPP_B23 48
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#define GSPI0_CLK_LOOPBK 49
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#define GSPI1_CLK_LOOPBK 50
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/* Group G */
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#define GPP_G0 51
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#define GPP_G1 52
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#define GPP_G2 53
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#define GPP_G3 54
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#define GPP_G4 55
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#define GPP_G5 56
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#define GPP_G6 57
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#define GPP_G7 58
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/* Group SPI */
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#define SPI0_IO_2 59
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#define SPI0_IO_3 60
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#define SPI0_MOSI 61
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#define SPI0_MISO 62
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#define SPI0_CS2_B 63
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#define SPI0_CS0_B 64
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#define SPI0_CS1_B 65
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#define SPI0_CLK 66
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#define SPI0_CLK_LOOPBK 67
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#define NUM_GPIO_COM0_PADS (SPI0_CLK_LOOPBK - GPP_A0 + 1)
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/* Group D */
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#define GPP_D0 68
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#define GPP_D1 69
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#define GPP_D2 70
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#define GPP_D3 71
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#define GPP_D4 72
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#define GPP_D5 73
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#define GPP_D6 74
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#define GPP_D7 75
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#define GPP_D8 76
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#define GPP_D9 77
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#define GPP_D10 78
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#define GPP_D11 79
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#define GPP_D12 80
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#define GPP_D13 81
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#define GPP_D14 82
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#define GPP_D15 83
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#define GPP_D16 84
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#define GPP_D17 85
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#define GPP_D18 86
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#define GPP_D19 87
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#define GPP_D20 88
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#define GPP_D21 89
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#define GPP_D22 90
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#define GPP_D23 91
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#define GSPI2_CLK_LOOPBK 92
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/* Group F */
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#define GPP_F0 93
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#define GPP_F1 94
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#define GPP_F2 95
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#define GPP_F3 96
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#define GPP_F4 97
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#define GPP_F5 98
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#define GPP_F6 99
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#define GPP_F7 100
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#define GPP_F8 101
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#define GPP_F9 102
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#define GPP_F10 103
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#define GPP_F11 104
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#define GPP_F12 105
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#define GPP_F13 106
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#define GPP_F14 107
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#define GPP_F15 108
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#define GPP_F16 109
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#define GPP_F17 110
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#define GPP_F18 111
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#define GPP_F19 112
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#define GPP_F20 113
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#define GPP_F21 114
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#define GPP_F22 115
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#define GPP_F23 116
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/* Group H */
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#define GPP_H0 117
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#define GPP_H1 118
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#define GPP_H2 119
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#define GPP_H3 120
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#define GPP_H4 121
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#define GPP_H5 122
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#define GPP_H6 123
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#define GPP_H7 124
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#define GPP_H8 125
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#define GPP_H9 126
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#define GPP_H10 127
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#define GPP_H11 128
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#define GPP_H12 129
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#define GPP_H13 130
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#define GPP_H14 131
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#define GPP_H15 132
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#define GPP_H16 133
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#define GPP_H17 134
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#define GPP_H18 135
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#define GPP_H19 136
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#define GPP_H20 137
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#define GPP_H21 138
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#define GPP_H22 139
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#define GPP_H23 140
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/* Group VGPIO 0 */
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#define CNV_BTEN 141
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#define CNV_GNEN 142
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#define CNV_WFEN 143
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#define CNV_WCEN 144
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#define CNV_BT_HOST_WAKE_B 145
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#define CNV_BT_IF_SELECT 146
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#define vCNV_BT_UART_TXD 147
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#define vCNV_BT_UART_RXD 148
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#define vCNV_BT_UART_CTS_B 149
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#define vCNV_BT_UART_RTS_B 150
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#define vCNV_MFUART1_TXD 151
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#define vCNV_MFUART1_RXD 152
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#define vCNV_MFUART1_CTS_B 153
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#define vCNV_MFUART1_RTS_B 154
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#define vCNV_GNSS_UART_TXD 155
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#define vCNV_GNSS_UART_RXD 156
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#define vCNV_GNSS_UART_CTS_B 157
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#define vCNV_GNSS_UART_RTS_B 158
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#define vUART0_TXD 159
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#define vUART0_RXD 160
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#define vUART0_CTS_B 161
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#define vUART0_RTS_B 162
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#define vISH_UART0_TXD 163
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#define vISH_UART0_RXD 164
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#define vISH_UART0_CTS_B 165
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#define vISH_UART0_RTS_B 166
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#define vISH_UART1_TXD 167
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#define vISH_UART1_RXD 168
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#define vISH_UART1_CTS_B 169
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#define vISH_UART1_RTS_B 170
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#define vCNV_BT_I2S_BCLK 171
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#define vCNV_BT_I2S_WS_SYNC 172
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/* Group VGPIO 1 */
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#define vCNV_BT_I2S_SDO 173
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#define vCNV_BT_I2S_SDI 174
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#define vSSP2_SCLK 175
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#define vSSP2_SFRM 176
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#define vSSP2_TXD 177
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#define vSSP2_RXD 178
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#define vCNV_GNSS_HOST_WAKE_B 179
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#define vSD3_CD_B 180
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#define NUM_GPIO_COM1_PADS (vSD3_CD_B - GPP_D0 + 1)
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/* Group C */
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#define GPP_C0 181
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#define GPP_C1 182
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#define GPP_C2 183
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#define GPP_C3 184
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#define GPP_C4 185
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#define GPP_C5 186
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#define GPP_C6 187
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#define GPP_C7 188
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#define GPP_C8 189
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#define GPP_C9 190
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#define GPP_C10 191
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#define GPP_C11 192
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#define GPP_C12 193
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#define GPP_C13 194
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#define GPP_C14 195
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#define GPP_C15 196
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#define GPP_C16 197
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#define GPP_C17 198
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#define GPP_C18 199
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#define GPP_C19 200
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#define GPP_C20 201
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#define GPP_C21 202
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#define GPP_C22 203
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#define GPP_C23 204
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/* Group E */
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#define GPP_E0 205
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#define GPP_E1 206
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#define GPP_E2 207
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#define GPP_E3 208
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#define GPP_E4 209
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#define GPP_E5 210
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#define GPP_E6 211
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#define GPP_E7 212
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#define GPP_E8 213
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#define GPP_E9 214
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#define GPP_E10 215
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#define GPP_E11 216
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#define GPP_E12 217
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#define GPP_E13 218
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#define GPP_E14 219
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#define GPP_E15 220
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#define GPP_E16 221
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#define GPP_E17 222
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#define GPP_E18 223
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#define GPP_E19 224
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#define GPP_E20 225
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#define GPP_E21 226
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#define GPP_E22 227
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#define GPP_E23 228
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/* Group Jtag */
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#define PCH_TDO 229
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#define PCH_JTAGX 230
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#define PROC_PRDY_B 231
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#define PROC_PREQ_B 232
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#define CPU_TRST_B 233
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#define PCH_TDI 234
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#define PCH_TMS 235
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#define PCH_TCK 236
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#define ITP_PMODE 237
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/* Group HVMOS */
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#define EDP_BKLTEN 238
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#define EDP_BKLTCTL 239
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#define EDP_VDDEN 240
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#define SYS_PWROK 241
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#define SYS_RESET_B 242
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#define CL_RST_B 243
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#define NUM_GPIO_COM4_PADS (CL_RST_B - GPP_C0 + 1)
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/* Group GPD */
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#define GPD0 244
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#define GPD1 245
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#define GPD2 246
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#define GPD3 247
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#define GPD4 248
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#define GPD5 249
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#define GPD6 250
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#define GPD7 251
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#define GPD8 252
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#define GPD9 253
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#define GPD10 254
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#define GPD11 255
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#define SLP_LAN_B 256
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#define SLP_SUS_B 257
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#define WAKE_B 258
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#define DRAM_RESET_B 259
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#define NUM_GPIO_COM2_PADS (DRAM_RESET_B - GPD0 + 1)
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/* Group AZA */
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#define HDA_BCLK 260
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#define HDA_RST_B 261
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#define HDA_SYNC 262
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#define HDA_SDO 263
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#define HDA_SDI0 264
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#define HDA_SDI1 265
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#define I2S1_SFRM 266
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#define I2S1_TXD 267
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/* Group CPU */
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#define HDACPU_SDI 268
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#define HDACPU_SDO 269
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#define HDACPU_SCLK 270
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#define PM_SYNC 271
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#define PECI_IO 272
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#define CPUPWRGD 273
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#define THRMTRIP_B 274
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#define PLTRST_CPU_B 275
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#define PM_DOWN 276
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#define TRIGGER_IN 277
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#define TRIGGER_OUT 278
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#define NUM_GPIO_COM3_PADS (TRIGGER_OUT - HDA_BCLK + 1)
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#define TOTAL_PADS 279
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#define SD_PWR_EN_PIN GPP_A17
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#define COMM_0 0
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#define COMM_1 1
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#define COMM_2 2
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#define COMM_3 3
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#define COMM_4 4
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#define TOTAL_GPIO_COMM 5
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#endif
src
soc
intel
cannonlake
include
soc
gpio_soc_defs.h
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