coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio_soc_defs.h
Go to the documentation of this file.
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef _SOC_CANNONLAKE_GPIO_SOC_DEFS_H_
4 #define _SOC_CANNONLAKE_GPIO_SOC_DEFS_H_
5 
6 /*
7  * Most of the fixed numbers and macros are based on the GPP groups.
8  * The GPIO groups are accessed through register blocks called
9  * communities.
10  */
11 #define GPP_A 0x0
12 #define GPP_B 0x1
13 #define GPP_G 0x2
14 #define GROUP_SPI 0x3
15 #define GPP_D 0x5
16 #define GPP_F 0x6
17 #define GPP_H 0x7
18 #define GROUP_VGPIO0 0x8
19 #define GROUP_VGPIO1 0x9
20 #define GPD 0xA
21 #define GROUP_AZA 0xB
22 #define GROUP_CPU 0xC
23 #define GPP_C 0x4
24 #define GPP_E 0xD
25 #define GROUP_JTAG 0xE
26 #define GROUP_HVMOS 0xF
27 
28 #define GPIO_MAX_NUM_PER_GROUP 24
29 
30 /*
31  * GPIOs are ordered monotonically increasing to match ACPI/OS driver.
32  */
33 
34 /* Group A */
35 #define GPP_A0 0
36 #define GPP_A1 1
37 #define GPP_A2 2
38 #define GPP_A3 3
39 #define GPP_A4 4
40 #define GPP_A5 5
41 #define GPP_A6 6
42 #define GPP_A7 7
43 #define GPP_A8 8
44 #define GPP_A9 9
45 #define GPP_A10 10
46 #define GPP_A11 11
47 #define GPP_A12 12
48 #define GPP_A13 13
49 #define GPP_A14 14
50 #define GPP_A15 15
51 #define GPP_A16 16
52 #define GPP_A17 17
53 #define GPP_A18 18
54 #define GPP_A19 19
55 #define GPP_A20 20
56 #define GPP_A21 21
57 #define GPP_A22 22
58 #define GPP_A23 23
59 #define ESPI_CLK_LOOPBK 24
60 /* Group B */
61 #define GPP_B0 25
62 #define GPP_B1 26
63 #define GPP_B2 27
64 #define GPP_B3 28
65 #define GPP_B4 29
66 #define GPP_B5 30
67 #define GPP_B6 31
68 #define GPP_B7 32
69 #define GPP_B8 33
70 #define GPP_B9 34
71 #define GPP_B10 35
72 #define GPP_B11 36
73 #define GPP_B12 37
74 #define GPP_B13 38
75 #define GPP_B14 39
76 #define GPP_B15 40
77 #define GPP_B16 41
78 #define GPP_B17 42
79 #define GPP_B18 43
80 #define GPP_B19 44
81 #define GPP_B20 45
82 #define GPP_B21 46
83 #define GPP_B22 47
84 #define GPP_B23 48
85 #define GSPI0_CLK_LOOPBK 49
86 #define GSPI1_CLK_LOOPBK 50
87 /* Group G */
88 #define GPP_G0 51
89 #define GPP_G1 52
90 #define GPP_G2 53
91 #define GPP_G3 54
92 #define GPP_G4 55
93 #define GPP_G5 56
94 #define GPP_G6 57
95 #define GPP_G7 58
96 /* Group SPI */
97 #define SPI0_IO_2 59
98 #define SPI0_IO_3 60
99 #define SPI0_MOSI 61
100 #define SPI0_MISO 62
101 #define SPI0_CS2_B 63
102 #define SPI0_CS0_B 64
103 #define SPI0_CS1_B 65
104 #define SPI0_CLK 66
105 #define SPI0_CLK_LOOPBK 67
106 
107 #define NUM_GPIO_COM0_PADS (SPI0_CLK_LOOPBK - GPP_A0 + 1)
108 
109 /* Group D */
110 #define GPP_D0 68
111 #define GPP_D1 69
112 #define GPP_D2 70
113 #define GPP_D3 71
114 #define GPP_D4 72
115 #define GPP_D5 73
116 #define GPP_D6 74
117 #define GPP_D7 75
118 #define GPP_D8 76
119 #define GPP_D9 77
120 #define GPP_D10 78
121 #define GPP_D11 79
122 #define GPP_D12 80
123 #define GPP_D13 81
124 #define GPP_D14 82
125 #define GPP_D15 83
126 #define GPP_D16 84
127 #define GPP_D17 85
128 #define GPP_D18 86
129 #define GPP_D19 87
130 #define GPP_D20 88
131 #define GPP_D21 89
132 #define GPP_D22 90
133 #define GPP_D23 91
134 #define GSPI2_CLK_LOOPBK 92
135 /* Group F */
136 #define GPP_F0 93
137 #define GPP_F1 94
138 #define GPP_F2 95
139 #define GPP_F3 96
140 #define GPP_F4 97
141 #define GPP_F5 98
142 #define GPP_F6 99
143 #define GPP_F7 100
144 #define GPP_F8 101
145 #define GPP_F9 102
146 #define GPP_F10 103
147 #define GPP_F11 104
148 #define GPP_F12 105
149 #define GPP_F13 106
150 #define GPP_F14 107
151 #define GPP_F15 108
152 #define GPP_F16 109
153 #define GPP_F17 110
154 #define GPP_F18 111
155 #define GPP_F19 112
156 #define GPP_F20 113
157 #define GPP_F21 114
158 #define GPP_F22 115
159 #define GPP_F23 116
160 /* Group H */
161 #define GPP_H0 117
162 #define GPP_H1 118
163 #define GPP_H2 119
164 #define GPP_H3 120
165 #define GPP_H4 121
166 #define GPP_H5 122
167 #define GPP_H6 123
168 #define GPP_H7 124
169 #define GPP_H8 125
170 #define GPP_H9 126
171 #define GPP_H10 127
172 #define GPP_H11 128
173 #define GPP_H12 129
174 #define GPP_H13 130
175 #define GPP_H14 131
176 #define GPP_H15 132
177 #define GPP_H16 133
178 #define GPP_H17 134
179 #define GPP_H18 135
180 #define GPP_H19 136
181 #define GPP_H20 137
182 #define GPP_H21 138
183 #define GPP_H22 139
184 #define GPP_H23 140
185 /* Group VGPIO 0 */
186 #define CNV_BTEN 141
187 #define CNV_GNEN 142
188 #define CNV_WFEN 143
189 #define CNV_WCEN 144
190 #define CNV_BT_HOST_WAKE_B 145
191 #define CNV_BT_IF_SELECT 146
192 #define vCNV_BT_UART_TXD 147
193 #define vCNV_BT_UART_RXD 148
194 #define vCNV_BT_UART_CTS_B 149
195 #define vCNV_BT_UART_RTS_B 150
196 #define vCNV_MFUART1_TXD 151
197 #define vCNV_MFUART1_RXD 152
198 #define vCNV_MFUART1_CTS_B 153
199 #define vCNV_MFUART1_RTS_B 154
200 #define vCNV_GNSS_UART_TXD 155
201 #define vCNV_GNSS_UART_RXD 156
202 #define vCNV_GNSS_UART_CTS_B 157
203 #define vCNV_GNSS_UART_RTS_B 158
204 #define vUART0_TXD 159
205 #define vUART0_RXD 160
206 #define vUART0_CTS_B 161
207 #define vUART0_RTS_B 162
208 #define vISH_UART0_TXD 163
209 #define vISH_UART0_RXD 164
210 #define vISH_UART0_CTS_B 165
211 #define vISH_UART0_RTS_B 166
212 #define vISH_UART1_TXD 167
213 #define vISH_UART1_RXD 168
214 #define vISH_UART1_CTS_B 169
215 #define vISH_UART1_RTS_B 170
216 #define vCNV_BT_I2S_BCLK 171
217 #define vCNV_BT_I2S_WS_SYNC 172
218 /* Group VGPIO 1 */
219 #define vCNV_BT_I2S_SDO 173
220 #define vCNV_BT_I2S_SDI 174
221 #define vSSP2_SCLK 175
222 #define vSSP2_SFRM 176
223 #define vSSP2_TXD 177
224 #define vSSP2_RXD 178
225 #define vCNV_GNSS_HOST_WAKE_B 179
226 #define vSD3_CD_B 180
227 
228 #define NUM_GPIO_COM1_PADS (vSD3_CD_B - GPP_D0 + 1)
229 
230 /* Group C */
231 #define GPP_C0 181
232 #define GPP_C1 182
233 #define GPP_C2 183
234 #define GPP_C3 184
235 #define GPP_C4 185
236 #define GPP_C5 186
237 #define GPP_C6 187
238 #define GPP_C7 188
239 #define GPP_C8 189
240 #define GPP_C9 190
241 #define GPP_C10 191
242 #define GPP_C11 192
243 #define GPP_C12 193
244 #define GPP_C13 194
245 #define GPP_C14 195
246 #define GPP_C15 196
247 #define GPP_C16 197
248 #define GPP_C17 198
249 #define GPP_C18 199
250 #define GPP_C19 200
251 #define GPP_C20 201
252 #define GPP_C21 202
253 #define GPP_C22 203
254 #define GPP_C23 204
255 /* Group E */
256 #define GPP_E0 205
257 #define GPP_E1 206
258 #define GPP_E2 207
259 #define GPP_E3 208
260 #define GPP_E4 209
261 #define GPP_E5 210
262 #define GPP_E6 211
263 #define GPP_E7 212
264 #define GPP_E8 213
265 #define GPP_E9 214
266 #define GPP_E10 215
267 #define GPP_E11 216
268 #define GPP_E12 217
269 #define GPP_E13 218
270 #define GPP_E14 219
271 #define GPP_E15 220
272 #define GPP_E16 221
273 #define GPP_E17 222
274 #define GPP_E18 223
275 #define GPP_E19 224
276 #define GPP_E20 225
277 #define GPP_E21 226
278 #define GPP_E22 227
279 #define GPP_E23 228
280 /* Group Jtag */
281 #define PCH_TDO 229
282 #define PCH_JTAGX 230
283 #define PROC_PRDY_B 231
284 #define PROC_PREQ_B 232
285 #define CPU_TRST_B 233
286 #define PCH_TDI 234
287 #define PCH_TMS 235
288 #define PCH_TCK 236
289 #define ITP_PMODE 237
290 /* Group HVMOS */
291 #define EDP_BKLTEN 238
292 #define EDP_BKLTCTL 239
293 #define EDP_VDDEN 240
294 #define SYS_PWROK 241
295 #define SYS_RESET_B 242
296 #define CL_RST_B 243
297 
298 #define NUM_GPIO_COM4_PADS (CL_RST_B - GPP_C0 + 1)
299 
300 /* Group GPD */
301 #define GPD0 244
302 #define GPD1 245
303 #define GPD2 246
304 #define GPD3 247
305 #define GPD4 248
306 #define GPD5 249
307 #define GPD6 250
308 #define GPD7 251
309 #define GPD8 252
310 #define GPD9 253
311 #define GPD10 254
312 #define GPD11 255
313 #define SLP_LAN_B 256
314 #define SLP_SUS_B 257
315 #define WAKE_B 258
316 #define DRAM_RESET_B 259
317 
318 #define NUM_GPIO_COM2_PADS (DRAM_RESET_B - GPD0 + 1)
319 
320 /* Group AZA */
321 #define HDA_BCLK 260
322 #define HDA_RST_B 261
323 #define HDA_SYNC 262
324 #define HDA_SDO 263
325 #define HDA_SDI0 264
326 #define HDA_SDI1 265
327 #define I2S1_SFRM 266
328 #define I2S1_TXD 267
329 /* Group CPU */
330 #define HDACPU_SDI 268
331 #define HDACPU_SDO 269
332 #define HDACPU_SCLK 270
333 #define PM_SYNC 271
334 #define PECI_IO 272
335 #define CPUPWRGD 273
336 #define THRMTRIP_B 274
337 #define PLTRST_CPU_B 275
338 #define PM_DOWN 276
339 #define TRIGGER_IN 277
340 #define TRIGGER_OUT 278
341 
342 #define NUM_GPIO_COM3_PADS (TRIGGER_OUT - HDA_BCLK + 1)
343 
344 #define TOTAL_PADS 279
345 
346 #define SD_PWR_EN_PIN GPP_A17
347 
348 #define COMM_0 0
349 #define COMM_1 1
350 #define COMM_2 2
351 #define COMM_3 3
352 #define COMM_4 4
353 #define TOTAL_GPIO_COMM 5
354 
355 #endif