coreboot
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amd_pci_int_defs.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef AMD_STONEYRIDGE_AMD_PCI_INT_DEFS_H
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#define AMD_STONEYRIDGE_AMD_PCI_INT_DEFS_H
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/*
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* PIRQ and device routing - these define the index into the
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* FCH PCI_INTR 0xC00/0xC01 interrupt routing table.
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*/
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#define PIRQ_NC 0x1f
/* Not Used */
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#define PIRQ_A 0x00
/* INT A */
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#define PIRQ_B 0x01
/* INT B */
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#define PIRQ_C 0x02
/* INT C */
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#define PIRQ_D 0x03
/* INT D */
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#define PIRQ_E 0x04
/* INT E */
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#define PIRQ_F 0x05
/* INT F */
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#define PIRQ_G 0x06
/* INT G */
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#define PIRQ_H 0x07
/* INT H */
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#define PIRQ_MISC 0x08
/* Miscellaneous IRQ Settings - See FCH Spec */
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#define PIRQ_MISC0 0x09
/* Miscellaneous0 IRQ Settings */
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#define PIRQ_MISC1 0x0a
/* Miscellaneous1 IRQ Settings */
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#define PIRQ_MISC2 0x0b
/* Miscellaneous2 IRQ Settings */
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#define PIRQ_SIRQA 0x0c
/* Serial IRQ INTA */
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#define PIRQ_SIRQB 0x0d
/* Serial IRQ INTB */
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#define PIRQ_SIRQC 0x0e
/* Serial IRQ INTC */
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#define PIRQ_SIRQD 0x0f
/* Serial IRQ INTD */
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#define PIRQ_SCI 0x10
/* SCI IRQ */
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#define PIRQ_SMBUS 0x11
/* SMBUS 14h.0 */
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#define PIRQ_ASF 0x12
/* ASF */
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#define PIRQ_HDA 0x13
/* HDA 14h.2 */
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#define PIRQ_FC 0x14
/* FC */
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#define PIRQ_PMON 0x16
/* Performance Monitor */
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#define PIRQ_SD 0x17
/* SD */
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#define PIRQ_SDIO 0x1a
/* SDIO */
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#define PIRQ_EHCI 0x30
/* USB EHCI 12h.0 */
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#define PIRQ_XHCI 0x34
/* USB XHCI 10h.0 */
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#define PIRQ_SATA 0x41
/* SATA 11h.0 */
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#define PIRQ_GPIO 0x62
/* GPIO Controller Interrupt */
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#define PIRQ_I2C0 0x70
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#define PIRQ_I2C1 0x71
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#define PIRQ_I2C2 0x72
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#define PIRQ_I2C3 0x73
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#define PIRQ_UART0 0x74
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#define PIRQ_UART1 0x75
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#endif
/* AMD_STONEYRIDGE_AMD_PCI_INT_DEFS_H */
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amd
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amd_pci_int_defs.h
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