coreboot
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amd_pci_int_defs.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef AMD_STONEYRIDGE_AMD_PCI_INT_DEFS_H
4 #define AMD_STONEYRIDGE_AMD_PCI_INT_DEFS_H
5 
6 /*
7  * PIRQ and device routing - these define the index into the
8  * FCH PCI_INTR 0xC00/0xC01 interrupt routing table.
9  */
10 
11 #define PIRQ_NC 0x1f /* Not Used */
12 #define PIRQ_A 0x00 /* INT A */
13 #define PIRQ_B 0x01 /* INT B */
14 #define PIRQ_C 0x02 /* INT C */
15 #define PIRQ_D 0x03 /* INT D */
16 #define PIRQ_E 0x04 /* INT E */
17 #define PIRQ_F 0x05 /* INT F */
18 #define PIRQ_G 0x06 /* INT G */
19 #define PIRQ_H 0x07 /* INT H */
20 #define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings - See FCH Spec */
21 #define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */
22 #define PIRQ_MISC1 0x0a /* Miscellaneous1 IRQ Settings */
23 #define PIRQ_MISC2 0x0b /* Miscellaneous2 IRQ Settings */
24 #define PIRQ_SIRQA 0x0c /* Serial IRQ INTA */
25 #define PIRQ_SIRQB 0x0d /* Serial IRQ INTB */
26 #define PIRQ_SIRQC 0x0e /* Serial IRQ INTC */
27 #define PIRQ_SIRQD 0x0f /* Serial IRQ INTD */
28 #define PIRQ_SCI 0x10 /* SCI IRQ */
29 #define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */
30 #define PIRQ_ASF 0x12 /* ASF */
31 #define PIRQ_HDA 0x13 /* HDA 14h.2 */
32 #define PIRQ_FC 0x14 /* FC */
33 #define PIRQ_PMON 0x16 /* Performance Monitor */
34 #define PIRQ_SD 0x17 /* SD */
35 #define PIRQ_SDIO 0x1a /* SDIO */
36 #define PIRQ_EHCI 0x30 /* USB EHCI 12h.0 */
37 #define PIRQ_XHCI 0x34 /* USB XHCI 10h.0 */
38 #define PIRQ_SATA 0x41 /* SATA 11h.0 */
39 #define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */
40 #define PIRQ_I2C0 0x70
41 #define PIRQ_I2C1 0x71
42 #define PIRQ_I2C2 0x72
43 #define PIRQ_I2C3 0x73
44 #define PIRQ_UART0 0x74
45 #define PIRQ_UART1 0x75
46 
47 #endif /* AMD_STONEYRIDGE_AMD_PCI_INT_DEFS_H */