coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
iomap.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _SOC_CANNONLAKE_IOMAP_H_
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#define _SOC_CANNONLAKE_IOMAP_H_
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/*
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* Memory-mapped I/O registers.
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*/
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#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000
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#define PCH_PRESERVED_BASE_SIZE 0x02000000
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#define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000
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#define PCH_TRACE_HUB_BASE_SIZE 0x00800000
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#define EARLY_I2C_BASE_ADDRESS 0xfe040000
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#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
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#define MCH_BASE_ADDRESS 0xfed10000
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#define MCH_BASE_SIZE 0x8000
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#define DMI_BASE_ADDRESS 0xfeda0000
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#define DMI_BASE_SIZE 0x1000
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#define EP_BASE_ADDRESS 0xfeda1000
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#define EP_BASE_SIZE 0x1000
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#define EDRAM_BASE_ADDRESS 0xfed80000
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#define EDRAM_BASE_SIZE 0x4000
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#define GFXVT_BASE_ADDRESS 0xfed90000
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#define GFXVT_BASE_SIZE 0x1000
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#define IPUVT_BASE_ADDRESS 0xfed92000
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#define IPUVT_BASE_SIZE 0x1000
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#define VTVC0_BASE_ADDRESS 0xfed91000
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#define VTVC0_BASE_SIZE 0x1000
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#define REG_BASE_ADDRESS 0xfc000000
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#define REG_BASE_SIZE 0x1000
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#define PCH_PWRM_BASE_ADDRESS 0xfe000000
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#define PCH_PWRM_BASE_SIZE 0x10000
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#define SPI_BASE_ADDRESS 0xfe010000
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#define EARLY_GSPI_BASE_ADDRESS 0xfe011000
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#define GPIO_BASE_SIZE 0x10000
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#define HECI1_BASE_ADDRESS 0xfeda2000
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/* PTT registers */
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#define PTT_TXT_BASE_ADDRESS 0xfed30800
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#define PTT_PRESENT 0x00070000
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#define VTD_BASE_ADDRESS 0xFED90000
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#define VTD_BASE_SIZE 0x00004000
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/*
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* I/O port address space
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*/
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#define SMBUS_BASE_ADDRESS 0x0efa0
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#define SMBUS_BASE_SIZE 0x20
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#define ACPI_BASE_ADDRESS 0x1800
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#define ACPI_BASE_SIZE 0x100
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#define TCO_BASE_ADDRESS 0x400
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#define TCO_BASE_SIZE 0x20
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#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS
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#define P2SB_SIZE (16 * MiB)
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#endif
src
soc
intel
cannonlake
include
soc
iomap.h
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