13 #define WAK_STS (1 << 15)
14 #define PCIEXPWAK_STS (1 << 14)
15 #define PRBTNOR_STS (1 << 11)
16 #define RTC_STS (1 << 10)
17 #define PWRBTN_STS (1 << 8)
18 #define GBL_STS (1 << 5)
19 #define BM_STS (1 << 4)
20 #define TMROF_STS (1 << 0)
22 #define PCIEXPWAK_DIS (1 << 14)
23 #define RTC_EN (1 << 10)
24 #define PWRBTN_EN (1 << 8)
25 #define GBL_EN (1 << 5)
26 #define TMROF_EN (1 << 0)
28 #define GBL_RLS (1 << 2)
29 #define BM_RLD (1 << 1)
30 #define SCI_EN (1 << 0)
33 #define XHCI_SMI_EN (1 << 31)
34 #define ME_SMI_EN (1 << 30)
35 #define ESPI_SMI_EN (1 << 28)
36 #define GPIO_UNLOCK_SMI_EN (1 << 27)
37 #define INTEL_USB2_EN (1 << 18)
38 #define LEGACY_USB2_EN (1 << 17)
39 #define PERIODIC_EN (1 << 14)
40 #define TCO_SMI_EN (1 << 13)
41 #define MCSMI_EN (1 << 11)
42 #define BIOS_RLS (1 << 7)
43 #define SWSMI_TMR_EN (1 << 6)
44 #define APMC_EN (1 << 5)
45 #define SLP_SMI_EN (1 << 4)
46 #define LEGACY_USB_EN (1 << 3)
47 #define BIOS_EN (1 << 2)
49 #define GBL_SMI_EN (1 << 0)
51 #define SMI_STS_BITS 32
52 #define XHCI_SMI_STS_BIT 31
53 #define ME_SMI_STS_BIT 30
54 #define ESPI_SMI_STS_BIT 28
55 #define GPIO_UNLOCK_SMI_STS_BIT 27
56 #define SPI_SMI_STS_BIT 26
57 #define SCC_SMI_STS_BIT 25
58 #define MONITOR_STS_BIT 21
59 #define PCI_EXP_SMI_STS_BIT 20
60 #define SMBUS_SMI_STS_BIT 16
61 #define SERIRQ_SMI_STS_BIT 15
62 #define PERIODIC_STS_BIT 14
63 #define TCO_STS_BIT 13
64 #define DEVMON_STS_BIT 12
65 #define MCSMI_STS_BIT 11
66 #define GPIO_STS_BIT 10
67 #define GPE0_STS_BIT 9
69 #define SWSMI_TMR_STS_BIT 6
71 #define SMI_ON_SLP_EN_STS_BIT 4
72 #define LEGACY_USB_STS_BIT 3
73 #define BIOS_STS_BIT 2
75 #define SWGPE_CTRL (1 << 1)
76 #define DEVACT_STS 0x44
79 #define GPE0_REG_MAX 4
80 #define GPE0_REG_SIZE 32
81 #define GPE0_STS(x) (0x60 + ((x) * 4))
86 #define GPE_STS_RSVD GPE_STD
87 #define WADT_STS (1 << 18)
88 #define GPIO_T2_STS (1 << 15)
89 #define ESPI_STS (1 << 14)
90 #define PME_B0_STS (1 << 13)
91 #define ME_SCI_STS (1 << 12)
92 #define PME_STS (1 << 11)
93 #define BATLOW_STS (1 << 10)
94 #define PCI_EXP_STS (1 << 9)
95 #define SMB_WAK_STS (1 << 7)
96 #define TCOSCI_STS (1 << 6)
97 #define SWGPE_STS (1 << 2)
98 #define HOT_PLUG_STS (1 << 1)
99 #define GPE0_EN(x) (0x70 + ((x) * 4))
100 #define WADT_EN (1 << 18)
101 #define GPIO_T2_EN (1 << 15)
102 #define ESPI_EN (1 << 14)
103 #define PME_B0_EN_BIT 13
104 #define PME_B0_EN (1 << PME_B0_EN_BIT)
105 #define ME_SCI_EN (1 << 12)
106 #define PME_EN (1 << 11)
107 #define BATLOW_EN (1 << 10)
108 #define PCI_EXP_EN (1 << 9)
109 #define TCOSCI_EN (1 << 6)
110 #define SWGPE_EN (1 << 2)
111 #define HOT_PLUG_EN (1 << 1)
125 #define ENABLE_SMI_PARAMS \
126 (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS)
128 #define PSS_RATIO_STEP 2
129 #define PSS_MAX_ENTRIES 8
130 #define PSS_LATENCY_TRANSITION 10
131 #define PSS_LATENCY_BUSMASTER 10
133 #if !defined(__ACPI__)
137 #include <soc/iomap.h>
138 #include <soc/smbus.h>
uint16_t get_pmbase(void)
struct chipset_power_state __packed
uint8_t * pmc_mmio_regs(void)
uint16_t smbus_tco_regs(void)
uint32_t prev_sleep_state