coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
onboard.h
Go to the documentation of this file.
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef ONBOARD_H
4 #define ONBOARD_H
5 
6 #include <mainboard/google/cyan/irqroute.h>
7 
8 /*
9  * Calculation of gpio based irq.
10  * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE
11  * Max direct irq (MAX_DIRECT_IRQ) is 114.
12  * Size of gpio banks are
13  * GPSW_SIZE = 98
14  * GPNC_SIZE = 73
15  * GPEC_SIZE = 27
16  * GPSE_SIZE = 86
17  */
18 
19 /* KBD: Gpio index in N bank */
20 #define BOARD_I8042_GPIO_INDEX 17
21 /* SCI: Gpio index in N bank */
22 #define BOARD_SCI_GPIO_INDEX 15
23 /* Trackpad: Gpio index in N bank */
24 #define BOARD_TRACKPAD_GPIO_INDEX 18
25 /* Touch: Gpio index in N bank */
26 #define BOARD_TOUCH_GPIO_INDEX 19
27 /* TI Audio: Gpio index in SW bank */
28 #define BOARD_JACK_TI_GPIO_INDEX 34
29 /* MAXIM Audio: Gpio index in SE bank */
30 #define BOARD_JACK_MAXIM_GPIO_INDEX 77
31 
32 #define BOARD_TRACKPAD_NAME "trackpad"
33 #define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1)
34 #define BOARD_TRACKPAD_I2C_BUS 5
35 #define BOARD_TRACKPAD_I2C_ADDR 0x15
36 
37 #define BOARD_TOUCHSCREEN_NAME "touchscreen"
38 #define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2)
39 #define BOARD_TOUCHSCREEN_I2C_BUS 0
40 #define BOARD_TOUCHSCREEN_I2C_ADDR 0x10
41 
42 /* SD CARD gpio */
43 #define SDCARD_CD 81
44 
45 #define AUDIO_CODEC_HID "193C9890"
46 #define AUDIO_CODEC_CID "193C9890"
47 #define AUDIO_CODEC_DDN "Maxim 98090 Codec "
48 #define AUDIO_CODEC_I2C_ADDR 0x10
49 
50 #define TI_SWITCH_HID "104C227E"
51 #define TI_SWITCH_CID "104C227E"
52 #define TI_SWITCH_DDN "TI SWITCH "
53 #define TI_SWITCH_I2C_ADDR 0x3B
54 
55 #define DPTF_CPU_PASSIVE 88
56 #define DPTF_CPU_CRITICAL 90
57 
58 #endif