coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
p2sb.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef _DENVERTON_NS_P2SB_H_
4 #define _DENVERTON_NS_P2SB_H_
5 
6 /* Generate MP-table IRQ numbers for PCI devices. */
7 #define IO_APIC0 1
8 
9 /* P2SB Bridge Registers (D31:F1) */
10 #define PCH_P2SB_DEV PCI_DEV(0, P2SB_DEV, P2SB_FUNC)
11 
12 /* IO/MEM BARs */
13 #define SBREG_LO 0x10
14 #define MASK_SBREG_LO 0xff000000
15 #define SBREG_HI 0x14
16 #define MASK_SBREG_HI 0xffffffff
17 
18 /* ITSS PCRs (PID:ITSS) */
19 #define PCR_ITSS_PIRQA_ROUT 0x3100
20 #define PCR_ITSS_PIRQB_ROUT 0x3101
21 #define PCR_ITSS_PIRQC_ROUT 0x3102
22 #define PCR_ITSS_PIRQD_ROUT 0x3103
23 #define PCR_ITSS_PIRQE_ROUT 0x3104
24 #define PCR_ITSS_PIRQF_ROUT 0x3105
25 #define PCR_ITSS_PIRQG_ROUT 0x3106
26 #define PCR_ITSS_PIRQH_ROUT 0x3107
27 
28 #define PCR_ITSS_PIR00 0x3140
29 #define PCR_ITSS_PIR01 0x3142
30 #define PCR_ITSS_PIR02 0x3144
31 #define PCR_ITSS_PIR03 0x3146
32 #define PCR_ITSS_PIR04 0x3148
33 #define PCR_ITSS_PIR05 0x314A
34 #define PCR_ITSS_PIR06 0x314C
35 #define PCR_ITSS_PIR07 0x314E
36 #define PCR_ITSS_PIR08 0x3150
37 #define PCR_ITSS_PIR09 0x3152
38 #define PCR_ITSS_PIR10 0x3154
39 #define PCR_ITSS_PIR11 0x3156
40 #define PCR_ITSS_PIR12 0x3158
41 
42 #define PCH_PCR_ITSS_GIC 0x31FC ///< General Interrupt Control
43 ///< Max IRQ entry size, 1 = 24 entry size, 0 = 120 entry size
44 #define PCH_PCR_ITSS_GIC_MAX_IRQ_24 \
45  (1 << 9)
46 #define PCH_PCR_ITSS_GIC_AME (1 << 17) ///< Alternate Access Mode Enable
47 #define PCH_PCR_ITSS_GIC_SPS (1 << 16) ///< Shutdown Policy Select
48 #define PCH_PCR_ITSS_IPC0 0x3200 ///< Interrupt Polarity Control 0
49 #define PCH_PCR_ITSS_IPC1 0x3204 ///< Interrupt Polarity Control 1
50 #define PCH_PCR_ITSS_IPC2 0x3208 ///< Interrupt Polarity Control 2
51 #define PCH_PCR_ITSS_IPC3 0x320C ///< Interrupt Polarity Control 3
52 
53 #endif /* _DENVERTON_NS_P2SB_H_ */