coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
clock.h
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1 /* Source : APQ8064 LK Boot */
2 /* SPDX-License-Identifier: BSD-3-Clause */
3 
4 #ifndef __IPQ860X_CLOCK_H_
5 #define __IPQ860X_CLOCK_H_
6 
7 #include <soc/iomap.h>
8 #include <types.h>
9 
10 /* UART clock @ 7.3728 MHz */
11 #define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
12 
13 /* UART specific definitions */
14 
15 #define Uart_ns_val NS(BIT_POS_31,BIT_POS_16,N_VALUE,M_VALUE, 5, 4, 3, 1, 2, 0,3)
16 #define Uart_clk_ns_mask (BM(BIT_POS_31, BIT_POS_16) | BM(BIT_POS_6, BIT_POS_0))
17 #define Uart_mnd_en_mask BIT(8) * !!(625)
18 #define Uart_en_mask BIT(11)
19 #define MD16(m, n) (BVAL(BIT_POS_31, BIT_POS_16, m) | BVAL(BIT_POS_15, BIT_POS_0, ~(n)))
20 #define Uart_ns_val_rumi NS(BIT_POS_31, BIT_POS_16, N_VALUE, M_VALUE, 5, 4, 3, 1, 2, 0,0)
21 #define GSBIn_UART_APPS_MD_REG(n) REG(0x29D0+(0x20*((n)-1)))
22 #define GSBIn_UART_APPS_NS_REG(n) REG(0x29D4+(0x20*((n)-1)))
23 #define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1)))
24 #define BB_PLL_ENA_SC0_REG REG(0x34C0)
25 #define BB_PLL8_STATUS_REG REG(0x3158)
26 #define REG(off) ((void *)(MSM_CLK_CTL_BASE + (off)))
27 #define PLL8_STATUS_BIT 16
28 
29 #define PLL_LOCK_DET_STATUS_REG REG(0x03420)
30 #define SFAB_AHB_S3_FCLK_CTL_REG REG(0x0216C)
31 #define CFPB_CLK_NS_REG REG(0x0264C)
32 #define CFPB0_HCLK_CTL_REG REG(0x02650)
33 #define SFAB_CFPB_S_HCLK_CTL_REG REG(0x026C0)
34 #define CFPB_SPLITTER_HCLK_CTL_REG REG(0x026E0)
35 #define EBI2_CLK_CTL_REG REG(0x03B00)
36 
37 #define USB30_MASTER_CLK_CTL_REG REG(0x3b24)
38 #define USB30_MASTER_CLK_MD REG(0x3b28)
39 #define USB30_MASTER_CLK_NS REG(0x3b2c)
40 #define USB30_1_MASTER_CLK_CTL_REG REG(0x3b34)
41 #define USB30_MOC_UTMI_CLK_MD REG(0x3b40)
42 #define USB30_MOC_UTMI_CLK_NS REG(0x3b44)
43 #define USB30_MOC_UTMI_CLK_CTL REG(0x3b48)
44 #define USB30_1_MOC_UTMI_CLK_CTL REG(0x3b4c)
45 #define USB30_RESET REG(0x3b50)
46 
47 #define ALWAYS_ON_CLK_BRANCH_ENA(i) ((i) << 8)
48 
49 #define CLK_BRANCH_ENA_MASK 0x00000010
50 #define CLK_BRANCH_ENA_ENABLE 0x00000010
51 #define CLK_BRANCH_ENA_DISABLE 0x00000000
52 #define CLK_BRANCH_ENA(i) ((i) << 4)
53 
54 /* Register: CFPB_CLK_NS */
55 #define CLK_DIV_MASK 0x00000003
56 #define CLK_DIV_DIV_1 0x00000000
57 #define CLK_DIV_DIV_2 0x00000001
58 #define CLK_DIV_DIV_3 0x00000002
59 #define CLK_DIV_DIV_4 0x00000003
60 #define CLK_DIV(i) ((i) << 0)
61 
62 #define MN_MODE_DUAL_EDGE 0x2
63 #define BIT_POS_31 31
64 #define BIT_POS_16 16
65 #define BIT_POS_6 6
66 #define BIT_POS_0 0
67 #define BIT_POS_15 15
68 
69 #define BM(m, l) (((((unsigned int)-1) << (31-m)) >> (31-m+l)) << l)
70 #define BVAL(m, l, val) (((val) << l) & BM(m, l))
71 
72 /* MD Registers */
73 #define MD4(m_lsb, m, n_lsb, n) \
74  (BVAL((m_lsb+3), m_lsb, m) | BVAL((n_lsb+3), n_lsb, ~(n)))
75 
76 #define MD8(m_lsb, m, n_lsb, n) \
77  (BVAL((m_lsb+7), m_lsb, m) | BVAL((n_lsb+7), n_lsb, ~(n)))
78 
79 /* NS Registers */
80 #define NS(n_msb, n_lsb, n, m, mde_lsb, d_msb, d_lsb, d, s_msb, s_lsb, s) \
81  (BVAL(n_msb, n_lsb, ~(n-m)) \
82  | (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n)) \
83  | BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
84 
85 #define NS_MM(n_msb, n_lsb, n, m, d_msb, d_lsb, d, s_msb, s_lsb, s) \
86  (BVAL(n_msb, n_lsb, ~(n-m)) | BVAL(d_msb, d_lsb, (d-1)) \
87  | BVAL(s_msb, s_lsb, s))
88 
89 #define NS_DIVSRC(d_msb , d_lsb, d, s_msb, s_lsb, s) \
90  (BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
91 
92 #define NS_DIV(d_msb , d_lsb, d) \
93  BVAL(d_msb, d_lsb, (d-1))
94 
95 #define NS_SRC_SEL(s_msb, s_lsb, s) \
96  BVAL(s_msb, s_lsb, s)
97 
98 #define GMAC_AHB_RESET 0x903E24
99 
100 #define SRC_SEL_PLL0 (0x2 << 0)
101 #define MNCNTR_MODE_DUAL_EDGE (0x2 << 5)
102 #define MNCNTR_ENABLE (0x1 << 8)
103 #define MNCNTR_RST_ACTIVE (0x1 << 7)
104 #define N_VAL 15
105 
106 #define GMAC_CORE_RESET(n) \
107  ((void *)(0x903CBC + ((n) * 0x20)))
108 
109 #define GMACSEC_CORE_RESET(n) \
110  ((void *)(0x903E28 + ((n - 1) * 4)))
111 
112 #define GMAC_COREn_CLCK_SRC_CTL(N) \
113  (0x00900000 + (0x3CA0 + (32*(N-1))))
114 
115 #define GMAC_COREn_CLCK_SRC0_MD(N) \
116  (0x00900000 + (0x3CA4 + (32*(N-1))))
117 
118 #define GMAC_COREn_CLCK_SRC1_MD(N) \
119  (0x00900000 + (0x3CA8 + (32*(N-1))))
120 
121 #define GMAC_COREn_CLCK_SRC0_NS(N) \
122  (0x00900000 + (0x3CAC + (32*(N-1))))
123 
124 #define GMAC_COREn_CLCK_SRC1_NS(N) \
125  (0x00900000 + (0x3CB0 + (32*(N-1))))
126 
127 #define DISABLE_DUAL_MN8_SEL (0)
128 #define DISABLE_CLK_LOW_PWR (0 << 2)
129 #define GMAC_CORE_CLCK_ROOT_ENABLE (1 << 1)
130 
131 /* GMAC_COREn_CLK_SRC[0,1]_MD register bits (Assuming 133MHz) */
132 #define GMAC_CORE_CLCK_M 0x32
133 #define GMAC_CORE_CLCK_D 0 /* NOT(2*D) value */
134 #define GMAC_CORE_CLCK_M_SHIFT 16
135 #define GMAC_CORE_CLCK_D_SHIFT 0
136 #define GMAC_CORE_CLCK_M_VAL (GMAC_CORE_CLCK_M << GMAC_CORE_CLCK_M_SHIFT)
137 #define GMAC_CORE_CLCK_D_VAL (GMAC_CORE_CLCK_D << GMAC_CORE_CLCK_D_SHIFT)
138 
139 /* GMAC_COREn_CLK_SRC[0,1]_NS register bits (Assuming 133MHz) */
140 #define GMAC_CORE_CLCK_N 0x4 /* NOT(N-M) value, N=301 */
141 #define GMAC_CORE_CLCK_N_SHIFT 16
142 #define GMAC_CORE_CLCK_N_VAL (GMAC_CORE_CLCK_N << GMAC_CORE_CLCK_N_SHIFT)
143 #define GMAC_CORE_CLCK_MNCNTR_EN 0x00000100 /* Enable M/N counter */
144 #define GMAC_CORE_CLCK_MNCNTR_RST 0x00000080 /* Activate reset for M/N counter */
145 #define GMAC_CORE_CLCK_MNCNTR_MODE_MASK 0x00000060 /* M/N counter mode mask */
146 #define GMAC_CORE_CLCK_MNCNTR_MODE_SHIFT 5
147 #define GMAC_CORE_CLCK_MNCNTR_MODE_DUAL (2 << GMAC_CORE_CLCK_MNCNTR_MODE_SHIFT) /* M/N counter mode dual-edge */
148 #define GMAC_CORE_CLCK_PRE_DIV_SEL_MASK 0x00000018 /* Pre divider select mask */
149 #define GMAC_CORE_CLCK_PRE_DIV_SEL_SHIFT 3
150 #define GMAC_CORE_CLCK_PRE_DIV_SEL_BYP (0 << GMAC_CORE_CLCK_PRE_DIV_SEL_SHIFT) /* Pre divider bypass */
151 #define GMAC_CORE_CLCK_SRC_SEL_MASK 0x00000007 /* clk source Mux select mask */
152 #define GMAC_CORE_CLCK_SRC_SEL_SHIFT 0
153 #define GMAC_CORE_CLCK_SRC_SEL_PLL0 (2 << GMAC_CORE_CLCK_SRC_SEL_SHIFT) /* output of clk source Mux is PLL0 */
154 #define GMAC_COREn_CLCK_CTL(N) (0x00900000 + (0x3CB4 + (32*(N-1))))
155 
156 #define GMAC_COREn_CLCK_INV_DISABLE (0 << 5)
157 #define GMAC_COREn_CLCK_BRANCH_ENA (1 << 4)
158 
159 /* Uart specific clock settings */
160 
161 void uart_pll_vote_clk_enable(unsigned int);
162 void uart_clock_config(unsigned int gsbi_port, unsigned int m, unsigned int n,
163  unsigned int d, unsigned int clk_dummy);
164 void nand_clock_config(void);
165 void usb_clock_config(void);
166 int audio_clock_config(unsigned int frequency);
167 
168 #endif /* __IPQ860X_CLOCK_H_ */
nand_clock_config
void nand_clock_config(void)
nand_clock_config - configure NAND controller clocks
Definition: clock.c:56
audio_clock_config
int audio_clock_config(unsigned int frequency)
Definition: lcc.c:260
uart_clock_config
void uart_clock_config(unsigned int blsp_uart, unsigned int m, unsigned int n, unsigned int d)
uart_clock_config - configures UART clocks
Definition: clock.c:17
uart_pll_vote_clk_enable
void uart_pll_vote_clk_enable(unsigned int)
uart_pll_vote_clk_enable - enables PLL8
Definition: clock.c:11
usb_clock_config
void usb_clock_config(void)
usb_clock_config - configure USB controller clocks and reset the controller
Definition: clock.c:68
m
#define m(clkreg, src_bits, pmcreg, dst_bits)