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i440bx.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef NORTHBRIDGE_INTEL_I440BX_I440BX_H
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#define NORTHBRIDGE_INTEL_I440BX_I440BX_H
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/*
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* Datasheet:
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* - Name: Intel 440BX AGPset: 82443BX Host Bridge/Controller
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* - URL: http://www.intel.com/design/chipsets/datashts/290633.htm
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* - PDF: http://www.intel.com/design/chipsets/datashts/29063301.pdf
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* - Order Number: 290633-001
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*/
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/*
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* Host-to-PCI Bridge Registers.
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* The values in parenthesis are the default values as per datasheet.
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* Any addresses between 0x00 and 0xff not listed below are either
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* Reserved or Intel Reserved and should not be touched.
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*/
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#define NBXCFG 0x50
/* 440BX Configuration (0x0000:00S0_0000_000S_0S00b). */
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#define DRAMC 0x57
/* DRAM Control (00S0_0000b). */
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#define DRAMT 0x58
/* DRAM Timing (0x03). */
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#define PAM 0x59
/* Programmable Attribute Map, 7 registers (0x00). */
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#define PAM0 0x59
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#define PAM1 0x5a
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#define PAM2 0x5b
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#define PAM3 0x5c
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#define PAM4 0x5d
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#define PAM5 0x5e
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#define PAM6 0x5f
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#define DRB 0x60
/* DRAM Row Boundary, 8 registers (0x01). */
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#define DRB0 0x60
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#define DRB1 0x61
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#define DRB2 0x62
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#define DRB3 0x63
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#define DRB4 0x64
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#define DRB5 0x65
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#define DRB6 0x66
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#define DRB7 0x67
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#define FDHC 0x68
/* Fixed SDRAM Hole Control (0x00). */
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#define MBSC 0x69
/* Memory Buffer Strength Control (0x0000-0000-0000). */
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#define SMRAM 0x72
/* System Management RAM Control (0x02). */
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#define ESMRAMC 0x73
/* Extended System Management RAM Control (0x38). */
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#define RPS 0x74
/* SDRAM Row Page Size (0x0000). */
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#define SDRAMC 0x76
/* SDRAM Control Register (0x0000). */
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#define PGPOL 0x78
/* Paging Policy Register (0x00). */
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#define PMCR 0x7a
/* Power Management Control Register (0000_S0S0b). */
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#define SCRR 0x7b
/* Suspend CBR Refresh Rate Register (0x0038). */
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#define EAP 0x80
/* Error Address Pointer Register (0x00000000). */
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#define ERRCMD 0x90
/* Error Command Register (0x80). */
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#define ERRSTS 0x91
/* Error Status (0x0000). */
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// TODO: AGP stuff.
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#define ACAPID 0xa0
/* AGP Capability Identifier (0x00100002 or 0x00000000) */
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#define AGPSTAT 0xa4
/* AGP Status Register (0x1f000203, read only) */
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#define AGPCMD 0xa8
/* AGP Command Register (0x00000000) */
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#define AGPCTRL 0xb0
/* AGP Control Register (0x00000000) */
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#define APSIZE 0xb4
/* Aperture Size Control Register (0x00) */
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#define ATTBASE 0xb8
/* Aperture Translation Table (0x00000000) */
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#define MBFS 0xca
/* Memory Buffer Frequency Select (0x000000). */
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#define BSPAD 0xd0
/* BIOS Scratch Pad (0x000..000). */
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#define BSPAD0 0xd0
/* These are free for our use. */
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#define BSPAD1 0xd1
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#define BSPAD2 0xd2
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#define BSPAD3 0xd3
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#define BSPAD4 0xd4
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#define BSPAD5 0xd5
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#define BSPAD6 0xd6
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#define BSPAD7 0xd7
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#define DWTC 0xe0
/* DRAM Write Thermal Throttling Control (0x000..000). */
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#define DRTC 0xe8
/* DRAM Read Thermal Throttling Control (0x000..000). */
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#define BUFFC 0xf0
/* Buffer Control Register (0x0000). */
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#define NB PCI_DEV(0, 0, 0)
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#endif
/* NORTHBRIDGE_INTEL_I440BX_I440BX_H */
src
northbridge
intel
i440bx
i440bx.h
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