34 .pclk_cdrex_ratio = 0x5,
36 0x00020018, 0x00030000, 0x00010042, 0x00000d70
38 .timing_ref = 0x000000bb,
39 .timing_row = 0x8c36660f,
40 .timing_data = 0x3630580b,
41 .timing_power = 0x41000a44,
42 .phy0_dqs = 0x08080808,
43 .phy1_dqs = 0x08080808,
44 .phy0_dq = 0x08080808,
45 .phy1_dq = 0x08080808,
48 .phy0_pulld_dqs = 0xf,
49 .phy1_pulld_dqs = 0xf,
51 .lpddr3_ctrl_phy_reset = 0x1,
52 .ctrl_start_point = 0x10,
99 .prechconfig_tp_cnt = 0xff,
109 .chips_per_channel = 2,
110 .chips_to_configure = 1,
113 .gate_leveling_enable = 0,
117 .frequency_mhz = 800,
138 .pclk_cdrex_ratio = 0x5,
140 0x00020018, 0x00030000, 0x00010000, 0x00000d70
142 .timing_ref = 0x000000bb,
143 .timing_row = 0x8c36660f,
144 .timing_data = 0x3630580b,
145 .timing_power = 0x41000a44,
146 .phy0_dqs = 0x08080808,
147 .phy1_dqs = 0x08080808,
148 .phy0_dq = 0x08080808,
149 .phy1_dq = 0x08080808,
152 .phy0_pulld_dqs = 0xf,
153 .phy1_pulld_dqs = 0xf,
155 .lpddr3_ctrl_phy_reset = 0x1,
156 .ctrl_start_point = 0x10,
203 .prechconfig_tp_cnt = 0xff,
213 .chips_per_channel = 2,
214 .chips_to_configure = 1,
217 .gate_leveling_enable = 1,
222 .frequency_mhz = 780,
243 .pclk_cdrex_ratio = 0x5,
245 0x00020018, 0x00030000, 0x00010042, 0x00000d70
247 .timing_ref = 0x000000bb,
248 .timing_row = 0x8c36660f,
249 .timing_data = 0x3630580b,
250 .timing_power = 0x41000a44,
251 .phy0_dqs = 0x08080808,
252 .phy1_dqs = 0x08080808,
253 .phy0_dq = 0x08080808,
254 .phy1_dq = 0x08080808,
257 .phy0_pulld_dqs = 0xf,
258 .phy1_pulld_dqs = 0xf,
260 .lpddr3_ctrl_phy_reset = 0x1,
261 .ctrl_start_point = 0x10,
308 .prechconfig_tp_cnt = 0xff,
318 .chips_per_channel = 2,
319 .chips_to_configure = 1,
322 .gate_leveling_enable = 0,
326 .frequency_mhz = 780,
347 .pclk_cdrex_ratio = 0x5,
349 0x00020018, 0x00030000, 0x00010000, 0x00000d70
351 .timing_ref = 0x000000bb,
352 .timing_row = 0x8c36660f,
353 .timing_data = 0x3630580b,
354 .timing_power = 0x41000a44,
355 .phy0_dqs = 0x08080808,
356 .phy1_dqs = 0x08080808,
357 .phy0_dq = 0x08080808,
358 .phy1_dq = 0x08080808,
361 .phy0_pulld_dqs = 0xf,
362 .phy1_pulld_dqs = 0xf,
364 .lpddr3_ctrl_phy_reset = 0x1,
365 .ctrl_start_point = 0x10,
412 .prechconfig_tp_cnt = 0xff,
422 .chips_per_channel = 2,
423 .chips_to_configure = 1,
426 .gate_leveling_enable = 1,
430 #define BOARD_ID0_GPIO 88
431 #define BOARD_ID1_GPIO 89
470 if (id0 < 0 ||
id1 < 0)
#define printk(level,...)
#define DMC_MEMCONTROL_MEM_TYPE_DDR3
#define IMP_OUTPUT_DRV_30_OHM
#define DMC_MEMCONTROL_NUM_CHIP_1
#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x)
#define DMC_MEMCONTROL_BL_8
#define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED
#define DMC_MEMCONTROL_MRR_BYTE_7_0
#define DMC_CONCONTROL_EMPTY_DISABLE
#define DMC_MEMCONTROL_TP_DISABLE
#define DMC_MEMCONTROL_CLK_STOP_DISABLE
#define DMC_MEMBASECONFIG_VAL(x)
#define DMC_CONCONTROL_AREF_EN_DISABLE
#define IMP_OUTPUT_DRV_40_OHM
#define DMC_MEMCONFIGx_CHIP_ROW_15
#define DMC_CONCONTROL_DFI_INIT_START_DISABLE
#define DMC_MEMCONTROL_DSREF_ENABLE
#define DMC_CONCONTROL_RD_FETCH_DISABLE
#define DMC_MEMCONFIGx_CHIP_COL_10
#define DMC_MEMCONTROL_DPWRDN_DISABLE
#define DMC_MEMCONTROL_PZQ_DISABLE
#define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE
#define DMC_MEMCONTROL_MEM_WIDTH_32BIT
#define DMC_CONCONTROL_TIMEOUT_LEVEL0
#define DMC_CONCONTROL_IO_PD_CON_DISABLE
#define DMC_MEMCONFIGx_CHIP_BANK_8
#define BIOS_CRIT
BIOS_CRIT - Recovery unlikely.
static int board_get_config(void)
@ DAISY_CONFIG_ELPIDA_EVT
@ DAISY_CONFIG_SAMSUNG_DVT
@ DAISY_CONFIG_SAMSUNG_MP
@ DAISY_CONFIG_ELPIDA_PVT
@ DAISY_CONFIG_SAMSUNG_EVT
@ DAISY_CONFIG_ELPIDA_DVT
@ DAISY_CONFIG_SAMSUNG_PVT
struct mem_timings * get_mem_timings(void)
Get the correct memory timings for our selected memory type and speed.
int gpio_read_mvl3(unsigned int gpio)
unsigned int frequency_mhz