7 #define WAK_STS (1 << 15)
8 #define PCIEXPWAK_STS (1 << 14)
9 #define PRBTNOR_STS (1 << 11)
10 #define RTC_STS (1 << 10)
11 #define PWRBTN_STS (1 << 8)
12 #define GBL_STS (1 << 5)
13 #define BM_STS (1 << 4)
14 #define TMROF_STS (1 << 0)
16 #define PCIEXPWAK_DIS (1 << 14)
17 #define RTC_EN (1 << 10)
18 #define PWRBTN_EN (1 << 8)
19 #define GBL_EN (1 << 5)
20 #define TMROF_EN (1 << 0)
22 #define GBL_RLS (1 << 2)
23 #define BM_RLD (1 << 1)
24 #define SCI_EN (1 << 0)
27 #define XHCI_SMI_EN (1 << 31)
28 #define ME_SMI_EN (1 << 30)
29 #define ESPI_SMI_EN (1 << 28)
30 #define GPIO_UNLOCK_SMI_EN (1 << 27)
31 #define INTEL_USB2_EN (1 << 18)
32 #define LEGACY_USB2_EN (1 << 17)
33 #define PERIODIC_EN (1 << 14)
34 #define TCO_SMI_EN (1 << 13)
35 #define MCSMI_EN (1 << 11)
36 #define BIOS_RLS (1 << 7)
37 #define SWSMI_TMR_EN (1 << 6)
38 #define APMC_EN (1 << 5)
39 #define SLP_SMI_EN (1 << 4)
40 #define LEGACY_USB_EN (1 << 3)
41 #define BIOS_EN (1 << 2)
43 #define GBL_SMI_EN (1 << 0)
45 #define SMI_STS_BITS 32
46 #define XHCI_SMI_STS_BIT 31
47 #define ME_SMI_STS_BIT 30
48 #define ESPI_SMI_STS_BIT 28
49 #define GPIO_UNLOCK_SMI_STS_BIT 27
50 #define SPI_SMI_STS_BIT 26
51 #define SCC_SMI_STS_BIT 25
52 #define MONITOR_STS_BIT 21
53 #define PCI_EXP_SMI_STS_BIT 20
54 #define SMBUS_SMI_STS_BIT 16
55 #define SERIRQ_SMI_STS_BIT 15
56 #define PERIODIC_STS_BIT 14
57 #define TCO_STS_BIT 13
58 #define DEVMON_STS_BIT 12
59 #define MCSMI_STS_BIT 11
60 #define GPIO_STS_BIT 10
61 #define GPE0_STS_BIT 9
63 #define SWSMI_TMR_STS_BIT 6
65 #define SMI_ON_SLP_EN_STS_BIT 4
66 #define LEGACY_USB_STS_BIT 3
67 #define BIOS_STS_BIT 2
69 #define SWGPE_CTRL (1 << 1)
70 #define DEVACT_STS 0x44
73 #define GPE0_REG_MAX 4
74 #define GPE0_REG_SIZE 32
75 #define GPE0_STS(x) (0x60 + ((x) * 4))
80 #define GPE_STS_RSVD GPE_STD
81 #define WADT_STS (1 << 18)
82 #define GPIO_T2_STS (1 << 15)
83 #define ESPI_STS (1 << 14)
84 #define PME_B0_STS (1 << 13)
85 #define ME_SCI_STS (1 << 12)
86 #define PME_STS (1 << 11)
87 #define BATLOW_STS (1 << 10)
88 #define PCI_EXP_STS (1 << 9)
89 #define SMB_WAK_STS (1 << 7)
90 #define TCOSCI_STS (1 << 6)
91 #define SWGPE_STS (1 << 2)
92 #define HOT_PLUG_STS (1 << 1)
93 #define GPE0_EN(x) (0x70 + ((x) * 4))
94 #define WADT_EN (1 << 18)
95 #define GPIO_T2_EN (1 << 15)
96 #define ESPI_EN (1 << 14)
97 #define PME_B0_EN_BIT 13
98 #define PME_B0_EN (1 << PME_B0_EN_BIT)
99 #define ME_SCI_EN (1 << 12)
100 #define PME_EN (1 << 11)
101 #define BATLOW_EN (1 << 10)
102 #define PCI_EXP_EN (1 << 9)
103 #define TCOSCI_EN (1 << 6)
104 #define SWGPE_EN (1 << 2)
105 #define HOT_PLUG_EN (1 << 1)
119 #define ENABLE_SMI_PARAMS \
120 (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS)
122 #define PSS_RATIO_STEP 2
123 #define PSS_MAX_ENTRIES 8
124 #define PSS_LATENCY_TRANSITION 10
125 #define PSS_LATENCY_BUSMASTER 10
127 #if !defined(__ACPI__)
131 #include <soc/iomap.h>
132 #include <soc/smbus.h>
uint16_t get_pmbase(void)
struct chipset_power_state __packed
uint8_t * pmc_mmio_regs(void)
uint16_t smbus_tco_regs(void)
uint32_t prev_sleep_state