coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
xhci.h
Go to the documentation of this file.
1
/* SPDX-License-Identifier: GPL-2.0-only */
2
3
#ifndef _SOC_XHCI_H
4
#define _SOC_XHCI_H
5
6
/* XHCI PCI Registers */
7
#define XHCI_PWR_CTL_STS 0x74
8
#define XHCI_USB2PR 0xd0
9
#define XHCI_USB2PRM 0xd4
10
#define XHCI_USB3PR 0xd8
11
#define XHCI_USB3PRM 0xdc
12
#define XHCI_USB2PDO 0xe4
13
#define XHCI_USB3PDO 0xe8
14
15
/* XHCI Memory Registers */
16
#define XHCI_USB3_PORTSC(port) (0x4e0 + (port * 0x10))
17
# define XHCI_USB3_PORTSC_CHST (0x7f << 17)
18
# define XHCI_USB3_PORTSC_WCE (1 << 25)
/* Wake on Connect */
19
# define XHCI_USB3_PORTSC_WDE (1 << 26)
/* Wake on Disconnect */
20
# define XHCI_USB3_PORTSC_WOE (1 << 27)
/* Wake on Overcurrent */
21
# define XHCI_USB3_PORTSC_WRC (1 << 19)
/* Warm Reset Complete */
22
# define XHCI_USB3_PORTSC_LWS (1 << 16)
/* Link Write Strobe */
23
# define XHCI_USB3_PORTSC_PED (1 << 1)
/* Port Enabled/Disabled */
24
# define XHCI_USB3_PORTSC_WPR (1 << 31)
/* Warm Port Reset */
25
# define XHCI_USB3_PORTSC_PLS (0xf << 5)
/* Port Link State */
26
# define XHCI_PLSR_DISABLED (4 << 5)
/* Port is disabled */
27
# define XHCI_PLSR_RXDETECT (5 << 5)
/* Port is disconnected */
28
# define XHCI_PLSR_POLLING (7 << 5)
/* Port is polling */
29
# define XHCI_PLSW_ENABLE (5 << 5)
/* Enable port */
30
31
#define XHCI_RESET_TIMEOUT 100000
/* 100ms */
32
33
#endif
/* _SOC_XHCI_H */
src
soc
intel
braswell
include
soc
xhci.h
Generated by
1.9.1