coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
nct6776.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /* Both NCT6776D and NCT6776F package variants are supported. */
4 
5 #ifndef SUPERIO_NUVOTON_NCT6776_H
6 #define SUPERIO_NUVOTON_NCT6776_H
7 
8 /* Logical Device Numbers (LDN). */
9 #define NCT6776_FDC 0x00 /* Floppy */
10 #define NCT6776_PP 0x01 /* Parallel port */
11 #define NCT6776_SP1 0x02 /* Com1 */
12 #define NCT6776_SP2 0x03 /* Com2 & IR */
13 #define NCT6776_KBC 0x05 /* PS/2 keyboard and mouse */
14 #define NCT6776_CIR 0x06
15 #define NCT6776_GPIO6789_V 0x07
16 #define NCT6776_WDT1_GPIO01A_V 0x08
17 #define NCT6776_GPIO1234567_V 0x09
18 #define NCT6776_ACPI 0x0A
19 #define NCT6776_HWM_FPLED 0x0B /* Hardware monitor & front LED */
20 #define NCT6776_VID 0x0D
21 #define NCT6776_CIRWKUP 0x0E /* CIR wakeup */
22 #define NCT6776_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open drain select */
23 #define NCT6776_SVID 0x14
24 #define NCT6776_DSLP 0x16 /* Deep sleep */
25 #define NCT6776_GPIOA_LDN 0x17
26 
27 /* virtual LDN for GPIO and WDT */
28 #define NCT6776_WDT1 ((0 << 8) | NCT6776_WDT1_GPIO01A_V)
29 
30 #define NCT6776_GPIOBASE ((3 << 8) | NCT6776_WDT1_GPIO01A_V)
31 
32 #define NCT6776_GPIO0 ((1 << 8) | NCT6776_WDT1_GPIO01A_V)
33 #define NCT6776_GPIO1 ((1 << 8) | NCT6776_GPIO1234567_V)
34 #define NCT6776_GPIO2 ((2 << 8) | NCT6776_GPIO1234567_V)
35 #define NCT6776_GPIO3 ((3 << 8) | NCT6776_GPIO1234567_V)
36 #define NCT6776_GPIO4 ((4 << 8) | NCT6776_GPIO1234567_V)
37 #define NCT6776_GPIO5 ((5 << 8) | NCT6776_GPIO1234567_V)
38 #define NCT6776_GPIO6 ((6 << 8) | NCT6776_GPIO1234567_V)
39 #define NCT6776_GPIO7 ((7 << 8) | NCT6776_GPIO1234567_V)
40 #define NCT6776_GPIO8 ((0 << 8) | NCT6776_GPIO6789_V)
41 #define NCT6776_GPIO9 ((1 << 8) | NCT6776_GPIO6789_V)
42 #define NCT6776_GPIOA ((2 << 8) | NCT6776_WDT1_GPIO01A_V)
43 
44 #endif /* SUPERIO_NUVOTON_NCT6776_H */