coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
nct6776.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* Both NCT6776D and NCT6776F package variants are supported. */
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#ifndef SUPERIO_NUVOTON_NCT6776_H
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#define SUPERIO_NUVOTON_NCT6776_H
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/* Logical Device Numbers (LDN). */
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#define NCT6776_FDC 0x00
/* Floppy */
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#define NCT6776_PP 0x01
/* Parallel port */
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#define NCT6776_SP1 0x02
/* Com1 */
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#define NCT6776_SP2 0x03
/* Com2 & IR */
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#define NCT6776_KBC 0x05
/* PS/2 keyboard and mouse */
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#define NCT6776_CIR 0x06
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#define NCT6776_GPIO6789_V 0x07
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#define NCT6776_WDT1_GPIO01A_V 0x08
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#define NCT6776_GPIO1234567_V 0x09
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#define NCT6776_ACPI 0x0A
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#define NCT6776_HWM_FPLED 0x0B
/* Hardware monitor & front LED */
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#define NCT6776_VID 0x0D
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#define NCT6776_CIRWKUP 0x0E
/* CIR wakeup */
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#define NCT6776_GPIO_PP_OD 0x0F
/* GPIO Push-Pull/Open drain select */
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#define NCT6776_SVID 0x14
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#define NCT6776_DSLP 0x16
/* Deep sleep */
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#define NCT6776_GPIOA_LDN 0x17
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/* virtual LDN for GPIO and WDT */
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#define NCT6776_WDT1 ((0 << 8) | NCT6776_WDT1_GPIO01A_V)
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#define NCT6776_GPIOBASE ((3 << 8) | NCT6776_WDT1_GPIO01A_V)
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#define NCT6776_GPIO0 ((1 << 8) | NCT6776_WDT1_GPIO01A_V)
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#define NCT6776_GPIO1 ((1 << 8) | NCT6776_GPIO1234567_V)
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#define NCT6776_GPIO2 ((2 << 8) | NCT6776_GPIO1234567_V)
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#define NCT6776_GPIO3 ((3 << 8) | NCT6776_GPIO1234567_V)
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#define NCT6776_GPIO4 ((4 << 8) | NCT6776_GPIO1234567_V)
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#define NCT6776_GPIO5 ((5 << 8) | NCT6776_GPIO1234567_V)
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#define NCT6776_GPIO6 ((6 << 8) | NCT6776_GPIO1234567_V)
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#define NCT6776_GPIO7 ((7 << 8) | NCT6776_GPIO1234567_V)
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#define NCT6776_GPIO8 ((0 << 8) | NCT6776_GPIO6789_V)
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#define NCT6776_GPIO9 ((1 << 8) | NCT6776_GPIO6789_V)
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#define NCT6776_GPIOA ((2 << 8) | NCT6776_WDT1_GPIO01A_V)
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#endif
/* SUPERIO_NUVOTON_NCT6776_H */
src
superio
nuvoton
nct6776
nct6776.h
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