coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
smi.h
Go to the documentation of this file.
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #ifndef AMD_STONEYRIDGE_SMI_H
4 #define AMD_STONEYRIDGE_SMI_H
5 
6 #define SMI_GEVENTS 24
7 #define SCIMAPS 59 /* 0..58 */
8 #define SCI_GPES 32
9 #define NUMBER_SMITYPES 160
10 
11 #define SMI_EVENT_STATUS 0x0
12 #define SMI_EVENT_ENABLE 0x04
13 #define SMI_SCI_TRIG 0x08
14 #define SMI_SCI_LEVEL 0x0c
15 #define SMI_SCI_STATUS 0x10
16 #define SMI_SCI_EN 0x14
17 #define SMI_SCI_MAP0 0x40
18 # define SMI_SCI_MAP(X) (SMI_SCI_MAP0 + (X))
19 
20 /* SMI source and status */
21 #define SMITYPE_AGPIO65 0
22 #define SMITYPE_AGPIO66 1
23 #define SMITYPE_AGPIO3 2
24 #define SMITYPE_LPCPME_AGPIO22 3
25 #define SMITYPE_GPIO4 4
26 #define SMITYPE_LPCPD_AGPIOG21 5
27 #define SMITYPE_IRTX1_G15 6
28 #define SMITYPE_AGPIO5_DEVSLP0 7
29 #define SMITYPE_WAKE_AGPIO2 8
30 #define SMITYPE_APIO68_SGPIOCLK 9
31 #define SMITYPE_AGPIO6 10
32 #define SMITYPE_GPIO7 11
33 #define SMITYPE_USBOC0_TRST_AGPIO16 12
34 #define SMITYPE_USB0C1_TDI_AGPIO17 13
35 #define SMITYPE_USBOC2_TCK_AGPIO18 14
36 #define SMITYPE_TDO_USB0C3_AGPIO24 15
37 #define SMITYPE_ACPRES_USBOC4_IRRX0_AGPIO23 16
38 /* 17 Reserved */
39 #define SMITYPE_BLINK_AGPIO11_USBOC7 18
40 #define SMITYPE_SYSRESET_AGPIO1 19
41 #define SMITYPE_IRRX1_AGPIO15 20
42 #define SMITYPE_IRTX0_USBOC5_AGPIO13 21
43 #define SMITYPE_GPIO9_SERPORTRX 22
44 #define SMITYPE_GPIO8_SEPORTTX 23
45 #define GEVENT_MASK ((1 << SMITYPE_AGPIO65) \
46  | (1 << SMITYPE_AGPIO66) \
47  | (1 << SMITYPE_AGPIO3) \
48  | (1 << SMITYPE_LPCPME_AGPIO22) \
49  | (1 << SMITYPE_GPIO4) \
50  | (1 << SMITYPE_LPCPD_AGPIOG21) \
51  | (1 << SMITYPE_IRTX1_G15) \
52  | (1 << SMITYPE_AGPIO5_DEVSLP0) \
53  | (1 << SMITYPE_WAKE_AGPIO2) \
54  | (1 << SMITYPE_APIO68_SGPIOCLK) \
55  | (1 << SMITYPE_AGPIO6) \
56  | (1 << SMITYPE_GPIO7) \
57  | (1 << SMITYPE_USBOC0_TRST_AGPIO16) \
58  | (1 << SMITYPE_USB0C1_TDI_AGPIO17) \
59  | (1 << SMITYPE_USBOC2_TCK_AGPIO18) \
60  | (1 << SMITYPE_TDO_USB0C3_AGPIO24) \
61  | (1 << SMITYPE_ACPRES_USBOC4_IRRX0_AGPIO23) \
62  | (1 << SMITYPE_BLINK_AGPIO11_USBOC7) \
63  | (1 << SMITYPE_SYSRESET_AGPIO1) \
64  | (1 << SMITYPE_IRRX1_AGPIO15) \
65  | (1 << SMITYPE_IRTX0_USBOC5_AGPIO13) \
66  | (1 << SMITYPE_GPIO9_SERPORTRX))
67 #define SMITYPE_EHCI0_WAKE 24
68 #define SMITYPE_EHCI1_WAKE 25
69 #define SMITYPE_ESPI_SYS 26
70 #define SMITYPE_ESPI_WAKE_PME 27
71 /* 28-32 Reserved */
72 #define SMITYPE_FCH_FAKE0 33
73 #define SMITYPE_FCH_FAKE1 34
74 #define SMITYPE_FCH_FAKE2 35
75 /* 36 Reserved */
76 #define SMITYPE_SATA_GEVENT0 37
77 #define SMITYPE_SATA_GEVENT1 38
78 #define SMITYPE_ACP_WAKE 39
79 #define SMITYPE_ECG 40
80 #define SMITYPE_GPIO_CTL 41
81 #define SMITYPE_CIR_PME 42
82 #define SMITYPE_ALT_HPET_ALARM 43
83 #define SMITYPE_FAN_THERMAL 44
84 #define SMITYPE_ASF_MASTER_SLAVE 45
85 #define SMITYPE_I2S_WAKE 46
86 #define SMITYPE_SMBUS0_MASTER 47
87 #define SMITYPE_TWARN 48
88 #define SMITYPE_TRAFFIC_MON 49
89 #define SMITYPE_ILLB 50
90 #define SMITYPE_PWRBUTTON_UP 51
91 #define SMITYPE_PROCHOT 52
92 #define SMITYPE_APU_HW 53
93 #define SMITYPE_NB_SCI 54
94 #define SMITYPE_RAS_SERR 55
95 #define SMITYPE_XHC0_PME 56
96 /* 57 Reserved */
97 #define SMITYPE_ACDC_TIMER 58
98 /* 59-62 Reserved */
99 #define SMITYPE_TEMP_TSI 63
100 #define SMITYPE_KB_RESET 64
101 #define SMITYPE_SLP_TYP 65
102 #define SMITYPE_AL2H_ACPI 66
103 #define SMITYPE_AHCI 67
104 /* 68-71 Reserved */
105 #define SMITYPE_GBL_RLS 72
106 #define SMITYPE_BIOS_RLS 73
107 #define SMITYPE_PWRBUTTON_DOWN 74
108 #define SMITYPE_SMI_CMD_PORT 75
109 #define SMITYPE_USB_SMI 76
110 #define SMITYPE_SERIRQ 77
111 #define SMITYPE_SMBUS0_INTR 78
112 #define SMITYPE_XHC_ERROR 80
113 #define SMITYPE_INTRUDER 81
114 #define SMITYPE_VBAT_LOW 82
115 #define SMITYPE_PROTHOT 83
116 #define SMITYPE_PCI_SERR 84
117 #define SMITYPE_GPP_SERR 85
118 /* 85-88 Reserved */
119 #define SMITYPE_TMERTRIP 89
120 #define SMITYPE_EMUL60_64 90
121 #define SMITYPE_USB_FLR 91
122 #define SMITYPE_SATA_FLR 92
123 #define SMITYPE_AZ_FLR 93
124 /* 94-132 Reserved */
125 #define SMITYPE_FANIN0 133
126 /* 134-137 Reserved */
127 #define SMITYPE_FAKE0 138
128 #define SMITYPE_FAKE1 139
129 #define SMITYPE_FAKE2 140
130 /* 141 Reserved */
131 #define SMITYPE_SHORT_TIMER 142
132 #define SMITYPE_LONG_TIMER 143
133 #define SMITYPE_AB_SMI 144
134 #define SMITYPE_SOFT_RESET 145
135 /* 146-147 Reserved */
136 #define SMITYPE_IOTRAP0 148
137 /* 149-151 Reserved */
138 #define SMITYPE_MEMTRAP0 152
139 /* 153-155 Reserved */
140 #define SMITYPE_CFGTRAP0 156
141 /* 157-159 Reserved */
142 
143 #define TYPE_TO_MASK(X) (1 << (X) % 32)
144 
145 #define SMI_REG_SMISTS0 0x80
146 #define SMI_REG_SMISTS1 0x84
147 #define SMI_REG_SMISTS2 0x88
148 #define SMI_REG_SMISTS3 0x8c
149 #define SMI_REG_SMISTS4 0x90
150 
151 #define SMI_REG_POINTER 0x94
152 # define SMI_STATUS_SRC_SCI (1 << 0)
153 # define SMI_STATUS_SRC_0 (1 << 1) /* SMIx80 */
154 # define SMI_STATUS_SRC_1 (1 << 2) /* SMIx84... */
155 # define SMI_STATUS_SRC_2 (1 << 3)
156 # define SMI_STATUS_SRC_3 (1 << 4)
157 # define SMI_STATUS_SRC_4 (1 << 5)
158 
159 #define SMI_TIMER 0x96
160 #define SMI_TIMER_MASK 0x7fff
161 #define SMI_TIMER_EN (1 << 15)
162 
163 #define SMI_REG_SMITRIG0 0x98
164 # define SMITRG0_EOS (1 << 28)
165 # define SMI_TIMER_SEL (1 << 29)
166 # define SMITRG0_SMIENB (1 << 31)
167 
168 #define SMI_REG_CONTROL0 0xa0
169 #define SMI_REG_CONTROL1 0xa4
170 #define SMI_REG_CONTROL2 0xa8
171 #define SMI_REG_CONTROL3 0xac
172 #define SMI_REG_CONTROL4 0xb0
173 #define SMI_REG_CONTROL5 0xb4
174 #define SMI_REG_CONTROL6 0xb8
175 #define SMI_REG_CONTROL7 0xbc
176 #define SMI_REG_CONTROL8 0xc0
177 #define SMI_REG_CONTROL9 0xc4
178 
179 #endif /* AMD_STONEYRIDGE_SMI_H */