coreboot
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i2c_pad_def.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef AMD_BLOCK_I2C_PAD_DEF_H
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#define AMD_BLOCK_I2C_PAD_DEF_H
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#include <types.h>
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/* MISC_I2Cx_PAD_CTRL and MISC_I23Cx_PAD_CTRL are in the same place, but have different bit
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definitions. Which one is present depends on the SoC. */
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#define MISC_I2C0_PAD_CTRL 0xd8
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#define MISC_I2C_PAD_CTRL(bus) (MISC_I2C0_PAD_CTRL + 4 * (bus))
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#define I2C_PAD_CTRL_NG_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
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#define I2C_PAD_CTRL_NG_NORMAL 0xc
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#define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) | BIT(5))
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#define I2C_PAD_CTRL_RX_SHIFT 4
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#define I2C_PAD_CTRL_RX_SEL_OFF (0 << I2C_PAD_CTRL_RX_SHIFT)
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#define I2C_PAD_CTRL_RX_SEL_3_3V (1 << I2C_PAD_CTRL_RX_SHIFT)
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#define I2C_PAD_CTRL_RX_SEL_1_8V (3 << I2C_PAD_CTRL_RX_SHIFT)
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#define I2C_PAD_CTRL_PULLDOWN_EN BIT(6)
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#define I2C_PAD_CTRL_FALLSLEW_MASK (BIT(7) | BIT(8))
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#define I2C_PAD_CTRL_FALLSLEW_SHIFT 7
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#define I2C_PAD_CTRL_FALLSLEW_STD (0 << I2C_PAD_CTRL_FALLSLEW_SHIFT)
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#define I2C_PAD_CTRL_FALLSLEW_LOW (1 << I2C_PAD_CTRL_FALLSLEW_SHIFT)
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#define I2C_PAD_CTRL_FALLSLEW_EN BIT(9)
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#define I2C_PAD_CTRL_SPIKE_RC_EN BIT(10)
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#define I2C_PAD_CTRL_SPIKE_RC_SEL BIT(11)
/* 0 = 50ns, 1 = 20ns */
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#define I2C_PAD_CTRL_CAP_DOWN BIT(12)
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#define I2C_PAD_CTRL_CAP_UP BIT(13)
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#define I2C_PAD_CTRL_RES_DOWN BIT(14)
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#define I2C_PAD_CTRL_RES_UP BIT(15)
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#define I2C_PAD_CTRL_BIAS_CRT_EN BIT(16)
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#define I2C_PAD_CTRL_SPARE0 BIT(17)
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#define I2C_PAD_CTRL_SPARE1 BIT(18)
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/* The following bits are reserved in Picasso and Cezanne */
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#define I2C_PAD_CTRL_PD_EN BIT(19)
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#define I2C_PAD_CTRL_COMP_SEL BIT(20)
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#define I2C_PAD_CTRL_RES_BIAS_EN BIT(21)
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#endif
/* AMD_BLOCK_I2C_PAD_DEF_H */
src
soc
amd
common
block
i2c
i2c_pad_def.h
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