coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio_soc_defs.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 #ifndef _SOC_TIGERLAKE_GPIO_SOC_DEFS_H_
3 #define _SOC_TIGERLAKE_GPIO_SOC_DEFS_H_
4 /*
5  * Most of the fixed numbers and macros are based on the GPP groups.
6  * The GPIO groups are accessed through register blocks called
7  * communities.
8  */
9 #define GPP_B 0x0
10 #define GPP_T 0x1
11 #define GPP_A 0x2
12 #define GPP_R 0x3
13 #define GPD 0x4
14 #define GPP_S 0x5
15 #define GPP_H 0x6
16 #define GPP_D 0x7
17 #define GPP_U 0x8
18 #define GPP_F 0xA
19 #define GPP_C 0xB
20 #define GPP_E 0xC
21 
22 #define GPIO_MAX_NUM_PER_GROUP 27
23 
24 #define COMM_0 0
25 #define COMM_1 1
26 #define COMM_2 2
27 /* GPIO community 3 is not exposed to be used and hence is skipped. */
28 #define COMM_4 3
29 #define COMM_5 4
30 /*
31  * GPIOs are ordered monotonically increasing to match ACPI/OS driver.
32  */
33 /* Group B */
34 #define GPP_B0 0
35 #define GPP_B1 1
36 #define GPP_B2 2
37 #define GPP_B3 3
38 #define GPP_B4 4
39 #define GPP_B5 5
40 #define GPP_B6 6
41 #define GPP_B7 7
42 #define GPP_B8 8
43 #define GPP_B9 9
44 #define GPP_B10 10
45 #define GPP_B11 11
46 #define GPP_B12 12
47 #define GPP_B13 13
48 #define GPP_B14 14
49 #define GPP_B15 15
50 #define GPP_B16 16
51 #define GPP_B17 17
52 #define GPP_B18 18
53 #define GPP_B19 19
54 #define GPP_B20 20
55 #define GPP_B21 21
56 #define GPP_B22 22
57 #define GPP_B23 23
58 #define GPP_B24 24 /* GSPI0_CLK_LOOPBK */
59 #define GPP_B25 25 /* GSPI1_CLK_LOOPBK */
60 
61 /* Group T */
62 #define GPP_T0 26
63 #define GPP_T1 27
64 #define GPP_T2 28
65 #define GPP_T3 29
66 #define GPP_T4 30
67 #define GPP_T5 31
68 #define GPP_T6 32
69 #define GPP_T7 33
70 #define GPP_T8 34
71 #define GPP_T9 35
72 #define GPP_T10 36
73 #define GPP_T11 37
74 #define GPP_T12 38
75 #define GPP_T13 39
76 #define GPP_T14 40
77 #define GPP_T15 41
78 
79 /* Group A */
80 #define GPP_A0 42
81 #define GPP_A1 43
82 #define GPP_A2 44
83 #define GPP_A3 45
84 #define GPP_A4 46
85 #define GPP_A5 47
86 #define GPP_A6 48
87 #define GPP_A7 49
88 #define GPP_A8 50
89 #define GPP_A9 51
90 #define GPP_A10 52
91 #define GPP_A11 53
92 #define GPP_A12 54
93 #define GPP_A13 55
94 #define GPP_A14 56
95 #define GPP_A15 57
96 #define GPP_A16 58
97 #define GPP_A17 59
98 #define GPP_A18 60
99 #define GPP_A19 61
100 #define GPP_A20 62
101 #define GPP_A21 63
102 #define GPP_A22 64
103 #define GPP_A23 65
104 #define GPP_A24 66 /* ESPI_CLK_LOOPBK */
105 
106 #define GPIO_COM0_START GPP_B0
107 #define GPIO_COM0_END GPP_A24
108 #define NUM_GPIO_COM0_PADS (GPP_A24 - GPP_B0 + 1)
109 
110 /* Group S */
111 #define GPP_S0 67
112 #define GPP_S1 68
113 #define GPP_S2 69
114 #define GPP_S3 70
115 #define GPP_S4 71
116 #define GPP_S5 72
117 #define GPP_S6 73
118 #define GPP_S7 74
119 
120 /* Group H */
121 #define GPP_H0 75
122 #define GPP_H1 76
123 #define GPP_H2 77
124 #define GPP_H3 78
125 #define GPP_H4 79
126 #define GPP_H5 80
127 #define GPP_H6 81
128 #define GPP_H7 82
129 #define GPP_H8 83
130 #define GPP_H9 84
131 #define GPP_H10 85
132 #define GPP_H11 86
133 #define GPP_H12 87
134 #define GPP_H13 88
135 #define GPP_H14 89
136 #define GPP_H15 90
137 #define GPP_H16 91
138 #define GPP_H17 92
139 #define GPP_H18 93
140 #define GPP_H19 94
141 #define GPP_H20 95
142 #define GPP_H21 96
143 #define GPP_H22 97
144 #define GPP_H23 98
145 
146 /* Group D */
147 #define GPP_D0 99
148 #define GPP_D1 100
149 #define GPP_D2 101
150 #define GPP_D3 102
151 #define GPP_D4 103
152 #define GPP_D5 104
153 #define GPP_D6 105
154 #define GPP_D7 106
155 #define GPP_D8 107
156 #define GPP_D9 108
157 #define GPP_D10 109
158 #define GPP_D11 110
159 #define GPP_D12 111
160 #define GPP_D13 112
161 #define GPP_D14 113
162 #define GPP_D15 114
163 #define GPP_D16 115
164 #define GPP_D17 116
165 #define GPP_D18 117
166 #define GPP_D19 118
167 #define GPP_GSPI2_CLK_LOOPBK 119
168 
169 /* Group U */
170 #define GPP_U0 120
171 #define GPP_U1 121
172 #define GPP_U2 122
173 #define GPP_U3 123
174 #define GPP_U4 124
175 #define GPP_U5 125
176 #define GPP_U6 126
177 #define GPP_U7 127
178 #define GPP_U8 128
179 #define GPP_U9 129
180 #define GPP_U10 130
181 #define GPP_U11 131
182 #define GPP_U12 132
183 #define GPP_U13 133
184 #define GPP_U14 134
185 #define GPP_U15 135
186 #define GPP_U16 136
187 #define GPP_U17 137
188 #define GPP_U18 138
189 #define GPP_U19 139
190 #define GPP_GSPI3_CLK_LOOPBK 140
191 #define GPP_GSPI4_CLK_LOOPBK 141
192 #define GPP_GSPI5_CLK_LOOPBK 142
193 #define GPP_GSPI6_CLK_LOOPBK 143
194 
195 /* Group VGPIO */
196 #define CNV_BTEN 144
197 #define CNV_BT_HOST_WAKEB 145
198 #define CNV_BT_IF_SELECT 146
199 #define vCNV_BT_UART_TXD 147
200 #define vCNV_BT_UART_RXD 148
201 #define vCNV_BT_UART_CTS_B 149
202 #define vCNV_BT_UART_RTS_B 150
203 #define vCNV_MFUART1_TXD 151
204 #define vCNV_MFUART1_RXD 152
205 #define vCNV_MFUART1_CTS_B 153
206 #define vCNV_MFUART1_RTS_B 154
207 #define vUART0_TXD 155
208 #define vUART0_RXD 156
209 #define vUART0_CTS_B 157
210 #define vUART0_RTS_B 158
211 #define vISH_UART0_TXD 159
212 #define vISH_UART0_RXD 160
213 #define vISH_UART0_CTS_B 161
214 #define vISH_UART0_RTS_B 162
215 #define vCNV_BT_I2S_BCLK 163
216 #define vCNV_BT_I2S_WS_SYNC 164
217 #define vCNV_BT_I2S_SDO 165
218 #define vCNV_BT_I2S_SDI 166
219 #define vI2S2_SCLK 167
220 #define vI2S2_SFRM 168
221 #define vI2S2_TXD 169
222 #define vI2S2_RXD 170
223 
224 #define GPIO_COM1_START GPP_S0
225 #define GPIO_COM1_END vI2S2_RXD
226 #define NUM_GPIO_COM1_PADS (vI2S2_RXD - GPP_S0 + 1)
227 
228 /* Group GPD */
229 #define GPD0 171
230 #define GPD1 172
231 #define GPD2 173
232 #define GPD3 174
233 #define GPD4 175
234 #define GPD5 176
235 #define GPD6 177
236 #define GPD7 178
237 #define GPD8 179
238 #define GPD9 180
239 #define GPD10 181
240 #define GPD11 182
241 #define GPD_INPUT3VSEL 183
242 #define GPD_SLP_LANB 184
243 #define GPD_SLP_SUSB 185
244 #define GPD_WAKEB 186
245 #define GPD_DRAM_RESETB 187
246 
247 #define GPIO_COM2_START GPD0
248 #define GPIO_COM2_END GPD_DRAM_RESETB
249 #define NUM_GPIO_COM2_PADS (GPD_DRAM_RESETB - GPD0 + 1)
250 
251 /* Group C */
252 #define GPP_C0 188
253 #define GPP_C1 189
254 #define GPP_C2 190
255 #define GPP_C3 191
256 #define GPP_C4 192
257 #define GPP_C5 193
258 #define GPP_C6 194
259 #define GPP_C7 195
260 #define GPP_C8 196
261 #define GPP_C9 197
262 #define GPP_C10 198
263 #define GPP_C11 199
264 #define GPP_C12 200
265 #define GPP_C13 201
266 #define GPP_C14 202
267 #define GPP_C15 203
268 #define GPP_C16 204
269 #define GPP_C17 205
270 #define GPP_C18 206
271 #define GPP_C19 207
272 #define GPP_C20 208
273 #define GPP_C21 209
274 #define GPP_C22 210
275 #define GPP_C23 211
276 
277 /* Group F */
278 #define GPP_F0 212
279 #define GPP_F1 213
280 #define GPP_F2 214
281 #define GPP_F3 215
282 #define GPP_F4 216
283 #define GPP_F5 217
284 #define GPP_F6 218
285 #define GPP_F7 219
286 #define GPP_F8 220
287 #define GPP_F9 221
288 #define GPP_F10 222
289 #define GPP_F11 223
290 #define GPP_F12 224
291 #define GPP_F13 225
292 #define GPP_F14 226
293 #define GPP_F15 227
294 #define GPP_F16 228
295 #define GPP_F17 229
296 #define GPP_F18 230
297 #define GPP_F19 231
298 #define GPP_F20 232
299 #define GPP_F21 233
300 #define GPP_F22 234
301 #define GPP_F23 235
302 #define GPP_F_CLK_LOOPBK 236
303 
304 /* Group HVCMOS */
305 #define GPP_L_BKLTEN 237
306 #define GPP_L_BKLTCTL 238
307 #define GPP_L_VDDEN 239
308 #define GPP_SYS_PWROK 240
309 #define GPP_SYS_RESETB 241
310 #define GPP_MLK_RSTB 242
311 
312 /* Group E */
313 #define GPP_E0 243
314 #define GPP_E1 244
315 #define GPP_E2 245
316 #define GPP_E3 246
317 #define GPP_E4 247
318 #define GPP_E5 248
319 #define GPP_E6 249
320 #define GPP_E7 250
321 #define GPP_E8 251
322 #define GPP_E9 252
323 #define GPP_E10 253
324 #define GPP_E11 254
325 #define GPP_E12 255
326 #define GPP_E13 256
327 #define GPP_E14 257
328 #define GPP_E15 258
329 #define GPP_E16 259
330 #define GPP_E17 260
331 #define GPP_E18 261
332 #define GPP_E19 262
333 #define GPP_E20 263
334 #define GPP_E21 264
335 #define GPP_E22 265
336 #define GPP_E23 266
337 #define GPP_E_CLK_LOOPBK 267
338 
339 /* Group JTAG */
340 #define GPP_JTAG_TDO 268
341 #define GPP_JTAG_X 269
342 #define GPP_JTAG_PRDYB 270
343 #define GPP_JTAG_PREQB 271
344 #define GPP_CPU_TRSTB 272
345 #define GPP_JTAG_TDI 273
346 #define GPP_JTAG_TMS 274
347 #define GPP_JTAG_TCK 275
348 #define GPP_DBG_PMODE 276
349 
350 #define GPIO_COM4_START GPP_C0
351 #define GPIO_COM4_END GPP_DBG_PMODE
352 #define NUM_GPIO_COM4_PADS (GPP_DBG_PMODE - GPP_C0 + 1)
353 
354 /* Group R */
355 #define GPP_R0 277
356 #define GPP_R1 278
357 #define GPP_R2 279
358 #define GPP_R3 280
359 #define GPP_R4 281
360 #define GPP_R5 282
361 #define GPP_R6 283
362 #define GPP_R7 284
363 
364 /* Group SPI */
365 #define GPP_SPI_IO_2 285
366 #define GPP_SPI_IO_3 286
367 #define GPP_SPI_MOSI_IO_0 287
368 #define GPP_SPI_MOSI_IO_1 288
369 #define GPP_SPI_TPM_CSB 289
370 #define GPP_SPI_FLASH_0_CSB 290
371 #define GPP_SPI_FLASH_1_CSB 291
372 #define GPP_SPI_CLK 292
373 #define GPP_CLK_LOOPBK 293
374 
375 #define GPIO_COM5_START GPP_R0
376 #define GPIO_COM5_END GPP_CLK_LOOPBK
377 #define NUM_GPIO_COM5_PADS (GPP_CLK_LOOPBK - GPP_R0 + 1)
378 
379 #define TOTAL_GPIO_COMM (COMM_5 + 1)
380 #define TOTAL_PADS 294
381 
382 #endif