coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
msr.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #ifndef _SOC_MSR_H_
4 #define _SOC_MSR_H_
5 
6 #include <intelblocks/msr.h>
7 
8 #define MSR_FEATURE_CONFIG 0x13c
9 #define FEATURE_CONFIG_LOCK BIT(0)
10 
11 #define IA32_MCG_CAP 0x179
12 #define IA32_MCG_CAP_COUNT_MASK 0xff
13 #define IA32_MCG_CAP_CTL_P_BIT 8
14 #define IA32_MCG_CAP_CTL_P_MASK (1 << IA32_MCG_CAP_CTL_P_BIT)
15 
16 #define IA32_MCG_CTL 0x17b
17 
18 /* IA32_MISC_ENABLE bits */
19 #define FAST_STRINGS_ENABLE_BIT (1 << 0)
20 #define SPEED_STEP_ENABLE_BIT (1 << 16)
21 #define MONIOR_ENABLE_BIT (1 << 18)
22 
23 #define MSR_IA32_ENERGY_PERF_BIAS 0x1b0
24 
25 /* MSR_PKG_CST_CONFIG_CONTROL bits */
26 #define MSR_PKG_CST_CONFIG_CONTROL 0xe2
27 #define PKG_CSTATE_LIMIT_SHIFT 0 /* 0:3 */
28 /* No package C-state limit. All C-States supported by the processor are available. */
29 #define PKG_CSTATE_LIMIT_MASK (0xf << PKG_CSTATE_LIMIT_SHIFT)
30 #define PKG_CSTATE_NO_LIMIT (0x7 << PKG_CSTATE_LIMIT_SHIFT)
31 #define CFG_LOCK_SHIFT 15
32 #define CFG_LOCK_ENABLE (1 << CFG_LOCK_SHIFT)
33 
34 /* MSR_POWER_CTL bits */
35 #define MSR_POWER_CTL 0x1fc
36 #define BIDIR_PROCHOT_ENABLE_SHIFT 0
37 #define BIDIR_PROCHOT_ENABLE (1 << BIDIR_PROCHOT_ENABLE_SHIFT)
38 #define FAST_BRK_SNP_ENABLE_SHIFT 3
39 #define FAST_BRK_SNP_ENABLE (1 << FAST_BRK_SNP_ENABLE_SHIFT)
40 #define FAST_BRK_INT_ENABLE_SHIFT 4
41 #define FAST_BRK_INT_ENABLE (1 << FAST_BRK_INT_ENABLE_SHIFT)
42 #define PHOLD_CST_PREVENTION_INIT_SHIFT 6
43 #define PHOLD_CST_PREVENTION_INIT_VALUE (1 << PHOLD_CST_PREVENTION_INIT_SHIFT)
44 #define ENERGY_PERF_BIAS_ACCESS_ENABLE_SHIFT 18
45 #define ENERGY_PERF_BIAS_ACCESS_ENABLE (1 << ENERGY_PERF_BIAS_ACCESS_ENABLE_SHIFT)
46 #define PROCHOT_OUTPUT_DISABLE_SHIFT 21
47 #define PROCHOT_OUTPUT_DISABLE (1 << PROCHOT_OUTPUT_DISABLE_SHIFT)
48 #define PWR_PERF_TUNING_DYN_SWITCHING_SHIFT 24
49 #define PWR_PERF_TUNING_DYN_SWITCHING_ENABLE (1 << PWR_PERF_TUNING_DYN_SWITCHING_SHIFT)
50 #define PROCHOT_LOCK_SHIFT 27
51 #define PROCHOT_LOCK_ENABLE (1 << PROCHOT_LOCK_SHIFT)
52 #define LTR_IIO_DISABLE_SHIFT 29
53 #define LTR_IIO_DISABLE (1 << LTR_IIO_DISABLE_SHIFT)
54 
55 /* MSR_IA32_PERF_CTRL (0x199) bits */
56 #define MSR_IA32_PERF_CTRL 0x199
57 #define PSTATE_REQ_SHIFT 8 /* 8:14 bits */
58 #define PSTATE_REQ_MASK (0x7f << PSTATE_REQ_SHIFT)
59 #define PSTATE_REQ_RATIO (0xa << PSTATE_REQ_SHIFT)
60 
61 /* MSR_MISC_PWR_MGMT bits */
62 #define MSR_MISC_PWR_MGMT 0x1aa
63 #define HWP_ENUM_SHIFT 6
64 #define HWP_ENUM_ENABLE (1 << HWP_ENUM_SHIFT)
65 #define HWP_EPP_SHIFT 12
66 #define HWP_EPP_ENUM_ENABLE (1 << HWP_EPP_SHIFT)
67 #define LOCK_MISC_PWR_MGMT_MSR_SHIFT 13
68 #define LOCK_MISC_PWR_MGMT_MSR (1 << LOCK_MISC_PWR_MGMT_MSR_SHIFT)
69 #define LOCK_THERM_INT_SHIFT 22
70 #define LOCK_THERM_INT (1 << LOCK_THERM_INT_SHIFT)
71 
72 /* MSR_TURBO_RATIO_LIMIT bits */
73 #define MSR_TURBO_RATIO_LIMIT 0x1ad
74 
75 /* MSR_TURBO_RATIO_LIMIT_CORES (0x1ae) */
76 #define MSR_TURBO_RATIO_LIMIT_CORES 0x1ae
77 
78 /* MSR_VR_CURRENT_CONFIG bits */
79 #define MSR_VR_CURRENT_CONFIG 0x601
80 #define CURRENT_LIMIT_LOCK_SHIFT 31
81 #define CURRENT_LIMIT_LOCK (0x1 << CURRENT_LIMIT_LOCK_SHIFT)
82 
83 /* MSR_TURBO_ACTIVATION_RATIO bits */
84 #define MSR_TURBO_ACTIVATION_RATIO 0x64c
85 #define MAX_NON_TURBO_RATIO_SHIFT 0
86 #define MAX_NON_TURBO_RATIO (0xff << MAX_NON_TURBO_RATIO_SHIFT)
87 
88 /* MSR_ENERGY_PERF_BIAS_CONFIG bits */
89 #define MSR_ENERGY_PERF_BIAS_CONFIG 0xa01
90 #define EPB_ENERGY_POLICY_SHIFT 3
91 #define EPB_ENERGY_POLICY_MASK (0xf << EPB_ENERGY_POLICY_SHIFT)
92 
93 /* MSR Protected Processor Inventory Number */
94 #define MSR_PPIN_CTL 0x04e
95 #define MSR_PPIN_CTL_LOCK 0x1
96 #define MSR_PPIN_CTL_ENABLE_SHIFT 1
97 #define MSR_PPIN_CTL_ENABLE (0x1 << MSR_PPIN_CTL_ENABLE_SHIFT)
98 #define MSR_PPIN 0x04f
99 #define MSR_PPIN_CAP_SHIFT 23
100 #define MSR_PPIN_CAP (0x1 << MSR_PPIN_CAP_SHIFT)
101 
102 #endif /* _SOC_MSR_H_ */