coreboot
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msr.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef _SOC_MSR_H_
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#define _SOC_MSR_H_
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#include <
intelblocks/msr.h
>
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#define MSR_FEATURE_CONFIG 0x13c
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#define FEATURE_CONFIG_LOCK BIT(0)
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#define IA32_MCG_CAP 0x179
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#define IA32_MCG_CAP_COUNT_MASK 0xff
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#define IA32_MCG_CAP_CTL_P_BIT 8
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#define IA32_MCG_CAP_CTL_P_MASK (1 << IA32_MCG_CAP_CTL_P_BIT)
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#define IA32_MCG_CTL 0x17b
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/* IA32_MISC_ENABLE bits */
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#define FAST_STRINGS_ENABLE_BIT (1 << 0)
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#define SPEED_STEP_ENABLE_BIT (1 << 16)
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#define MONIOR_ENABLE_BIT (1 << 18)
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#define MSR_IA32_ENERGY_PERF_BIAS 0x1b0
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/* MSR_PKG_CST_CONFIG_CONTROL bits */
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#define MSR_PKG_CST_CONFIG_CONTROL 0xe2
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#define PKG_CSTATE_LIMIT_SHIFT 0
/* 0:3 */
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/* No package C-state limit. All C-States supported by the processor are available. */
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#define PKG_CSTATE_LIMIT_MASK (0xf << PKG_CSTATE_LIMIT_SHIFT)
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#define PKG_CSTATE_NO_LIMIT (0x7 << PKG_CSTATE_LIMIT_SHIFT)
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#define CFG_LOCK_SHIFT 15
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#define CFG_LOCK_ENABLE (1 << CFG_LOCK_SHIFT)
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/* MSR_POWER_CTL bits */
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#define MSR_POWER_CTL 0x1fc
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#define BIDIR_PROCHOT_ENABLE_SHIFT 0
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#define BIDIR_PROCHOT_ENABLE (1 << BIDIR_PROCHOT_ENABLE_SHIFT)
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#define FAST_BRK_SNP_ENABLE_SHIFT 3
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#define FAST_BRK_SNP_ENABLE (1 << FAST_BRK_SNP_ENABLE_SHIFT)
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#define FAST_BRK_INT_ENABLE_SHIFT 4
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#define FAST_BRK_INT_ENABLE (1 << FAST_BRK_INT_ENABLE_SHIFT)
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#define PHOLD_CST_PREVENTION_INIT_SHIFT 6
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#define PHOLD_CST_PREVENTION_INIT_VALUE (1 << PHOLD_CST_PREVENTION_INIT_SHIFT)
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#define ENERGY_PERF_BIAS_ACCESS_ENABLE_SHIFT 18
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#define ENERGY_PERF_BIAS_ACCESS_ENABLE (1 << ENERGY_PERF_BIAS_ACCESS_ENABLE_SHIFT)
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#define PROCHOT_OUTPUT_DISABLE_SHIFT 21
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#define PROCHOT_OUTPUT_DISABLE (1 << PROCHOT_OUTPUT_DISABLE_SHIFT)
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#define PWR_PERF_TUNING_DYN_SWITCHING_SHIFT 24
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#define PWR_PERF_TUNING_DYN_SWITCHING_ENABLE (1 << PWR_PERF_TUNING_DYN_SWITCHING_SHIFT)
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#define PROCHOT_LOCK_SHIFT 27
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#define PROCHOT_LOCK_ENABLE (1 << PROCHOT_LOCK_SHIFT)
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#define LTR_IIO_DISABLE_SHIFT 29
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#define LTR_IIO_DISABLE (1 << LTR_IIO_DISABLE_SHIFT)
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/* MSR_IA32_PERF_CTRL (0x199) bits */
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#define MSR_IA32_PERF_CTRL 0x199
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#define PSTATE_REQ_SHIFT 8
/* 8:14 bits */
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#define PSTATE_REQ_MASK (0x7f << PSTATE_REQ_SHIFT)
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#define PSTATE_REQ_RATIO (0xa << PSTATE_REQ_SHIFT)
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/* MSR_MISC_PWR_MGMT bits */
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#define MSR_MISC_PWR_MGMT 0x1aa
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#define HWP_ENUM_SHIFT 6
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#define HWP_ENUM_ENABLE (1 << HWP_ENUM_SHIFT)
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#define HWP_EPP_SHIFT 12
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#define HWP_EPP_ENUM_ENABLE (1 << HWP_EPP_SHIFT)
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#define LOCK_MISC_PWR_MGMT_MSR_SHIFT 13
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#define LOCK_MISC_PWR_MGMT_MSR (1 << LOCK_MISC_PWR_MGMT_MSR_SHIFT)
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#define LOCK_THERM_INT_SHIFT 22
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#define LOCK_THERM_INT (1 << LOCK_THERM_INT_SHIFT)
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/* MSR_TURBO_RATIO_LIMIT bits */
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#define MSR_TURBO_RATIO_LIMIT 0x1ad
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/* MSR_TURBO_RATIO_LIMIT_CORES (0x1ae) */
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#define MSR_TURBO_RATIO_LIMIT_CORES 0x1ae
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/* MSR_VR_CURRENT_CONFIG bits */
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#define MSR_VR_CURRENT_CONFIG 0x601
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#define CURRENT_LIMIT_LOCK_SHIFT 31
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#define CURRENT_LIMIT_LOCK (0x1 << CURRENT_LIMIT_LOCK_SHIFT)
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/* MSR_TURBO_ACTIVATION_RATIO bits */
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#define MSR_TURBO_ACTIVATION_RATIO 0x64c
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#define MAX_NON_TURBO_RATIO_SHIFT 0
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#define MAX_NON_TURBO_RATIO (0xff << MAX_NON_TURBO_RATIO_SHIFT)
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/* MSR_ENERGY_PERF_BIAS_CONFIG bits */
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#define MSR_ENERGY_PERF_BIAS_CONFIG 0xa01
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#define EPB_ENERGY_POLICY_SHIFT 3
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#define EPB_ENERGY_POLICY_MASK (0xf << EPB_ENERGY_POLICY_SHIFT)
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/* MSR Protected Processor Inventory Number */
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#define MSR_PPIN_CTL 0x04e
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#define MSR_PPIN_CTL_LOCK 0x1
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#define MSR_PPIN_CTL_ENABLE_SHIFT 1
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#define MSR_PPIN_CTL_ENABLE (0x1 << MSR_PPIN_CTL_ENABLE_SHIFT)
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#define MSR_PPIN 0x04f
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#define MSR_PPIN_CAP_SHIFT 23
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#define MSR_PPIN_CAP (0x1 << MSR_PPIN_CAP_SHIFT)
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#endif
/* _SOC_MSR_H_ */
msr.h
src
soc
intel
xeon_sp
include
soc
msr.h
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