coreboot
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gpio_defs.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef _SOC_ALDERLAKE_GPIO_DEFS_H_
4 #define _SOC_ALDERLAKE_GPIO_DEFS_H_
5 
6 #ifndef __ACPI__
7 #include <stddef.h>
8 #endif
9 #include <soc/gpio_soc_defs.h>
10 
11 #define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */
12 
13 #define NUM_GPIO_COMx_GPI_REGS(n) \
14  (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
15 
16 #define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS)
17 #define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS)
18 #define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS)
19 #define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS)
20 #define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS)
21 #define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS)
22 
23 #define NUM_GPI_STATUS_REGS \
24  ((NUM_GPIO_COM0_GPI_REGS) +\
25  (NUM_GPIO_COM1_GPI_REGS) +\
26  (NUM_GPIO_COM2_GPI_REGS) +\
27  (NUM_GPIO_COM4_GPI_REGS) +\
28  (NUM_GPIO_COM5_GPI_REGS))
29 
30 #define PAD_CFG_LOCK_OFFSET 0x80
31 
32 /*
33  * IOxAPIC IRQs for the GPIOs
34  */
35 
36 /* Group T */
37 #define GPP_T0_IRQ 0x30
38 #define GPP_T1_IRQ 0x31
39 #define GPP_T2_IRQ 0x32
40 #define GPP_T3_IRQ 0x33
41 #define GPP_T4_IRQ 0x34
42 #define GPP_T5_IRQ 0x35
43 #define GPP_T6_IRQ 0x36
44 #define GPP_T7_IRQ 0x37
45 #define GPP_T8_IRQ 0x38
46 #define GPP_T9_IRQ 0x39
47 #define GPP_T10_IRQ 0x3A
48 #define GPP_T11_IRQ 0x3B
49 #define GPP_T12_IRQ 0x3C
50 #define GPP_T13_IRQ 0x3D
51 #define GPP_T14_IRQ 0x3E
52 #define GPP_T15_IRQ 0x3F
53 
54 /* Group A */
55 #define GPP_A0_IRQ 0x40
56 #define GPP_A1_IRQ 0x41
57 #define GPP_A2_IRQ 0x42
58 #define GPP_A3_IRQ 0x43
59 #define GPP_A4_IRQ 0x44
60 #define GPP_A5_IRQ 0x45
61 #define GPP_A6_IRQ 0x46
62 #define GPP_A7_IRQ 0x47
63 #define GPP_A8_IRQ 0x48
64 #define GPP_A9_IRQ 0x49
65 #define GPP_A10_IRQ 0x4A
66 #define GPP_A11_IRQ 0x4B
67 #define GPP_A12_IRQ 0x4C
68 #define GPP_A13_IRQ 0x4D
69 #define GPP_A14_IRQ 0x4E
70 #define GPP_A15_IRQ 0x4F
71 #define GPP_A16_IRQ 0x50
72 #define GPP_A17_IRQ 0x51
73 #define GPP_A18_IRQ 0x52
74 #define GPP_A19_IRQ 0x53
75 #define GPP_A20_IRQ 0x54
76 #define GPP_A21_IRQ 0x55
77 #define GPP_A22_IRQ 0x56
78 #define GPP_A23_IRQ 0x57
79 
80 /* Group B */
81 #define GPP_B0_IRQ 0x18
82 #define GPP_B1_IRQ 0x19
83 #define GPP_B2_IRQ 0x1A
84 #define GPP_B3_IRQ 0x1B
85 #define GPP_B4_IRQ 0x1C
86 #define GPP_B5_IRQ 0x1D
87 #define GPP_B6_IRQ 0x1E
88 #define GPP_B7_IRQ 0x1F
89 #define GPP_B8_IRQ 0x20
90 #define GPP_B9_IRQ 0x21
91 #define GPP_B10_IRQ 0x22
92 #define GPP_B11_IRQ 0x23
93 #define GPP_B12_IRQ 0x24
94 #define GPP_B13_IRQ 0x25
95 #define GPP_B14_IRQ 0x26
96 #define GPP_B15_IRQ 0x27
97 #define GPP_B16_IRQ 0x28
98 #define GPP_B17_IRQ 0x29
99 #define GPP_B18_IRQ 0x2A
100 #define GPP_B19_IRQ 0x2B
101 #define GPP_B20_IRQ 0x2C
102 #define GPP_B21_IRQ 0x2D
103 #define GPP_B22_IRQ 0x2E
104 #define GPP_B23_IRQ 0x2F
105 
106 /* Group C */
107 #define GPP_C0_iIRQ 0x6E
108 #define GPP_C1_IRQ 0x6F
109 #define GPP_C2_IRQ 0x70
110 #define GPP_C3_IRQ 0x71
111 #define GPP_C4_IRQ 0x72
112 #define GPP_C5_IRQ 0x73
113 #define GPP_C6_IRQ 0x74
114 #define GPP_C7_IRQ 0x75
115 #define GPP_C8_IRQ 0x76
116 #define GPP_C9_IRQ 0x77
117 #define GPP_C10_IRQ 0x18
118 #define GPP_C11_IRQ 0x19
119 #define GPP_C12_IRQ 0x1A
120 #define GPP_C13_IRQ 0x1B
121 #define GPP_C14_IRQ 0x1C
122 #define GPP_C15_IRQ 0x1D
123 #define GPP_C16_IRQ 0x1E
124 #define GPP_C17_IRQ 0x1F
125 #define GPP_C18_IRQ 0x20
126 #define GPP_C19_IRQ 0x21
127 #define GPP_C20_IRQ 0x22
128 #define GPP_C21_IRQ 0x23
129 #define GPP_C22_IRQ 0x24
130 #define GPP_C23_IRQ 0x25
131 
132 #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
133 /* Group D */
134 #define GPP_D0_IRQ 0x40
135 #define GPP_D1_IRQ 0x41
136 #define GPP_D2_IRQ 0x42
137 #define GPP_D3_IRQ 0x43
138 #define GPP_D4_IRQ 0x44
139 #define GPP_D5_IRQ 0x45
140 #define GPP_D6_IRQ 0x46
141 #define GPP_D7_IRQ 0x47
142 #define GPP_D8_IRQ 0x48
143 #define GPP_D9_IRQ 0x49
144 #define GPP_D10_IRQ 0x4A
145 #define GPP_D11_IRQ 0x4B
146 #define GPP_D12_IRQ 0x4C
147 #define GPP_D13_IRQ 0x4D
148 #define GPP_D14_IRQ 0x4E
149 #define GPP_D15_IRQ 0x4F
150 #define GPP_D16_IRQ 0x50
151 #define GPP_D17_IRQ 0x51
152 #define GPP_D18_IRQ 0x52
153 #define GPP_D19_IRQ 0x53
154 #else
155 /* Group D */
156 #define GPP_D0_IRQ 0x2C
157 #define GPP_D1_IRQ 0x2D
158 #define GPP_D2_IRQ 0x2E
159 #define GPP_D3_IRQ 0x2F
160 #define GPP_D4_IRQ 0x30
161 #define GPP_D5_IRQ 0x31
162 #define GPP_D6_IRQ 0x32
163 #define GPP_D7_IRQ 0x33
164 #define GPP_D8_IRQ 0x34
165 #define GPP_D9_IRQ 0x35
166 #define GPP_D10_IRQ 0x36
167 #define GPP_D11_IRQ 0x37
168 #define GPP_D12_IRQ 0x38
169 #define GPP_D13_IRQ 0x39
170 #define GPP_D14_IRQ 0x3A
171 #define GPP_D15_IRQ 0x3B
172 #define GPP_D16_IRQ 0x3C
173 #define GPP_D17_IRQ 0x3D
174 #define GPP_D18_IRQ 0x3E
175 #define GPP_D19_IRQ 0x3F
176 #endif
177 
178 /* Group E */
179 #define GPP_E0_IRQ 0x26
180 #define GPP_E1_IRQ 0x27
181 #define GPP_E2_IRQ 0x28
182 #define GPP_E3_IRQ 0x29
183 #define GPP_E4_IRQ 0x30
184 #define GPP_E5_IRQ 0x31
185 #define GPP_E6_IRQ 0x32
186 #define GPP_E7_IRQ 0x33
187 #define GPP_E8_IRQ 0x34
188 #define GPP_E9_IRQ 0x35
189 #define GPP_E10_IRQ 0x36
190 #define GPP_E11_IRQ 0x37
191 #define GPP_E12_IRQ 0x38
192 #define GPP_E13_IRQ 0x39
193 #define GPP_E14_IRQ 0x3A
194 #define GPP_E15_IRQ 0x3B
195 #define GPP_E16_IRQ 0x3C
196 #define GPP_E17_IRQ 0x3D
197 #define GPP_E18_IRQ 0x3E
198 #define GPP_E19_IRQ 0x3F
199 #define GPP_E20_IRQ 0x40
200 #define GPP_E21_IRQ 0x41
201 #define GPP_E22_IRQ 0x42
202 #define GPP_E23_IRQ 0x43
203 
204 /* Group F */
205 #define GPP_F0_IRQ 0x56
206 #define GPP_F1_IRQ 0x57
207 #define GPP_F2_IRQ 0x58
208 #define GPP_F3_IRQ 0x59
209 #define GPP_F4_IRQ 0x5A
210 #define GPP_F5_IRQ 0x5B
211 #define GPP_F6_IRQ 0x5C
212 #define GPP_F7_IRQ 0x5D
213 #define GPP_F8_IRQ 0x5E
214 #define GPP_F9_IRQ 0x5F
215 #define GPP_F10_IRQ 0x60
216 #define GPP_F11_IRQ 0x61
217 #define GPP_F12_IRQ 0x62
218 #define GPP_F13_IRQ 0x63
219 #define GPP_F14_IRQ 0x64
220 #define GPP_F15_IRQ 0x65
221 #define GPP_F16_IRQ 0x66
222 #define GPP_F17_IRQ 0x67
223 #define GPP_F18_IRQ 0x68
224 #define GPP_F19_IRQ 0x69
225 #define GPP_F20_IRQ 0x6A
226 #define GPP_F21_IRQ 0x6B
227 #define GPP_F22_IRQ 0x6C
228 #define GPP_F23_IRQ 0x6D
229 
230 #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
231 /* Group H */
232 #define GPP_H0_IRQ 0x28
233 #define GPP_H1_IRQ 0x29
234 #define GPP_H2_IRQ 0x2A
235 #define GPP_H3_IRQ 0x2B
236 #define GPP_H4_IRQ 0x2C
237 #define GPP_H5_IRQ 0x2D
238 #define GPP_H6_IRQ 0x2E
239 #define GPP_H7_IRQ 0x2F
240 #define GPP_H8_IRQ 0x30
241 #define GPP_H9_IRQ 0x31
242 #define GPP_H10_IRQ 0x32
243 #define GPP_H11_IRQ 0x33
244 #define GPP_H12_IRQ 0x34
245 #define GPP_H13_IRQ 0x35
246 #define GPP_H14_IRQ 0x36
247 #define GPP_H15_IRQ 0x37
248 #define GPP_H16_IRQ 0x38
249 #define GPP_H17_IRQ 0x39
250 #define GPP_H18_IRQ 0x3A
251 #define GPP_H19_IRQ 0x3B
252 #define GPP_H20_IRQ 0x3C
253 #define GPP_H21_IRQ 0x3D
254 #define GPP_H22_IRQ 0x3E
255 #define GPP_H23_IRQ 0x3F
256 
257 /* Group I */
258 #define GPP_I0_IRQ 0x74
259 #define GPP_I1_IRQ 0x75
260 #define GPP_I2_IRQ 0x76
261 #define GPP_I3_IRQ 0x77
262 #define GPP_I4_IRQ 0x18
263 #define GPP_I5_IRQ 0x19
264 #define GPP_I6_IRQ 0x1A
265 #define GPP_I7_IRQ 0x1B
266 #define GPP_I8_IRQ 0x1C
267 #define GPP_I9_IRQ 0x1D
268 #define GPP_I10_IRQ 0x1E
269 #define GPP_I11_IRQ 0x1F
270 #define GPP_I12_IRQ 0x20
271 #define GPP_I13_IRQ 0x21
272 #define GPP_I14_IRQ 0x22
273 #define GPP_I15_IRQ 0x23
274 #define GPP_I16_IRQ 0x24
275 #define GPP_I17_IRQ 0x25
276 #define GPP_I18_IRQ 0x26
277 #define GPP_I19_IRQ 0x27
278 #else
279 /* Group H */
280 #define GPP_H0_IRQ 0x74
281 #define GPP_H1_IRQ 0x75
282 #define GPP_H2_IRQ 0x76
283 #define GPP_H3_IRQ 0x77
284 #define GPP_H4_IRQ 0x18
285 #define GPP_H5_IRQ 0x19
286 #define GPP_H6_IRQ 0x1A
287 #define GPP_H7_IRQ 0x1B
288 #define GPP_H8_IRQ 0x1C
289 #define GPP_H9_IRQ 0x1D
290 #define GPP_H10_IRQ 0x1E
291 #define GPP_H11_IRQ 0x1F
292 #define GPP_H12_IRQ 0x20
293 #define GPP_H13_IRQ 0x21
294 #define GPP_H14_IRQ 0x22
295 #define GPP_H15_IRQ 0x23
296 #define GPP_H16_IRQ 0x24
297 #define GPP_H17_IRQ 0x25
298 #define GPP_H18_IRQ 0x26
299 #define GPP_H19_IRQ 0x27
300 #define GPP_H20_IRQ 0x28
301 #define GPP_H21_IRQ 0x29
302 #define GPP_H22_IRQ 0x2A
303 #define GPP_H23_IRQ 0x2B
304 #endif
305 
306 /* Group R */
307 #define GPP_R0_IRQ 0x58
308 #define GPP_R1_IRQ 0x59
309 #define GPP_R2_IRQ 0x5A
310 #define GPP_R3_IRQ 0x5B
311 #define GPP_R4_IRQ 0x5C
312 #define GPP_R5_IRQ 0x5D
313 #define GPP_R6_IRQ 0x5E
314 #define GPP_R7_IRQ 0x5F
315 
316 /* Group S */
317 #define GPP_S0_IRQ 0x6C
318 #define GPP_S1_IRQ 0x6D
319 #define GPP_S2_IRQ 0x6E
320 #define GPP_S3_IRQ 0x6F
321 #define GPP_S4_IRQ 0x70
322 #define GPP_S5_IRQ 0x71
323 #define GPP_S6_IRQ 0x72
324 #define GPP_S7_IRQ 0x73
325 
326 /* Group GPD */
327 #define GPD0_IRQ 0x60
328 #define GPD1_IRQ 0x61
329 #define GPD2_IRQ 0x62
330 #define GPD3_IRQ 0x63
331 #define GPD4_IRQ 0x64
332 #define GPD5_IRQ 0x65
333 #define GPD6_IRQ 0x66
334 #define GPD7_IRQ 0x67
335 #define GPD8_IRQ 0x68
336 #define GPD9_IRQ 0x69
337 #define GPD10_IRQ 0x6A
338 #define GPD11_IRQ 0x6B
339 
340 /* Register defines. */
341 #define GPIO_MISCCFG 0x10
342 #define GPE_DW_SHIFT 8
343 #define GPE_DW_MASK 0xfff00
344 #define HOSTSW_OWN_REG_0 0xb0
345 #define GPI_INT_STS_0 0x100
346 #define GPI_INT_EN_0 0x110
347 #define GPI_SMI_STS_0 0x180
348 #define GPI_SMI_EN_0 0x1A0
349 #define PAD_CFG_BASE 0x700
350 
351 #endif