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gpio_defs.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _SOC_ALDERLAKE_GPIO_DEFS_H_
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#define _SOC_ALDERLAKE_GPIO_DEFS_H_
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#ifndef __ACPI__
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#include <
stddef.h
>
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#endif
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#include <soc/gpio_soc_defs.h>
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#define GPIO_NUM_PAD_CFG_REGS 4
/* DW0, DW1, DW2, DW3 */
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#define NUM_GPIO_COMx_GPI_REGS(n) \
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(ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
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#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS)
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#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS)
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#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS)
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#define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS)
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#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS)
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#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS)
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#define NUM_GPI_STATUS_REGS \
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((NUM_GPIO_COM0_GPI_REGS) +\
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(NUM_GPIO_COM1_GPI_REGS) +\
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(NUM_GPIO_COM2_GPI_REGS) +\
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(NUM_GPIO_COM4_GPI_REGS) +\
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(NUM_GPIO_COM5_GPI_REGS))
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#define PAD_CFG_LOCK_OFFSET 0x80
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/*
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* IOxAPIC IRQs for the GPIOs
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*/
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/* Group T */
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#define GPP_T0_IRQ 0x30
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#define GPP_T1_IRQ 0x31
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#define GPP_T2_IRQ 0x32
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#define GPP_T3_IRQ 0x33
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#define GPP_T4_IRQ 0x34
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#define GPP_T5_IRQ 0x35
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#define GPP_T6_IRQ 0x36
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#define GPP_T7_IRQ 0x37
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#define GPP_T8_IRQ 0x38
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#define GPP_T9_IRQ 0x39
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#define GPP_T10_IRQ 0x3A
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#define GPP_T11_IRQ 0x3B
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#define GPP_T12_IRQ 0x3C
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#define GPP_T13_IRQ 0x3D
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#define GPP_T14_IRQ 0x3E
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#define GPP_T15_IRQ 0x3F
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/* Group A */
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#define GPP_A0_IRQ 0x40
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#define GPP_A1_IRQ 0x41
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#define GPP_A2_IRQ 0x42
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#define GPP_A3_IRQ 0x43
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#define GPP_A4_IRQ 0x44
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#define GPP_A5_IRQ 0x45
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#define GPP_A6_IRQ 0x46
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#define GPP_A7_IRQ 0x47
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#define GPP_A8_IRQ 0x48
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#define GPP_A9_IRQ 0x49
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#define GPP_A10_IRQ 0x4A
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#define GPP_A11_IRQ 0x4B
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#define GPP_A12_IRQ 0x4C
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#define GPP_A13_IRQ 0x4D
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#define GPP_A14_IRQ 0x4E
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#define GPP_A15_IRQ 0x4F
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#define GPP_A16_IRQ 0x50
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#define GPP_A17_IRQ 0x51
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#define GPP_A18_IRQ 0x52
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#define GPP_A19_IRQ 0x53
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#define GPP_A20_IRQ 0x54
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#define GPP_A21_IRQ 0x55
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#define GPP_A22_IRQ 0x56
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#define GPP_A23_IRQ 0x57
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/* Group B */
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#define GPP_B0_IRQ 0x18
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#define GPP_B1_IRQ 0x19
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#define GPP_B2_IRQ 0x1A
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#define GPP_B3_IRQ 0x1B
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#define GPP_B4_IRQ 0x1C
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#define GPP_B5_IRQ 0x1D
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#define GPP_B6_IRQ 0x1E
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#define GPP_B7_IRQ 0x1F
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#define GPP_B8_IRQ 0x20
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#define GPP_B9_IRQ 0x21
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#define GPP_B10_IRQ 0x22
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#define GPP_B11_IRQ 0x23
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#define GPP_B12_IRQ 0x24
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#define GPP_B13_IRQ 0x25
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#define GPP_B14_IRQ 0x26
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#define GPP_B15_IRQ 0x27
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#define GPP_B16_IRQ 0x28
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#define GPP_B17_IRQ 0x29
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#define GPP_B18_IRQ 0x2A
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#define GPP_B19_IRQ 0x2B
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#define GPP_B20_IRQ 0x2C
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#define GPP_B21_IRQ 0x2D
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#define GPP_B22_IRQ 0x2E
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#define GPP_B23_IRQ 0x2F
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/* Group C */
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#define GPP_C0_iIRQ 0x6E
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#define GPP_C1_IRQ 0x6F
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#define GPP_C2_IRQ 0x70
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#define GPP_C3_IRQ 0x71
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#define GPP_C4_IRQ 0x72
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#define GPP_C5_IRQ 0x73
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#define GPP_C6_IRQ 0x74
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#define GPP_C7_IRQ 0x75
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#define GPP_C8_IRQ 0x76
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#define GPP_C9_IRQ 0x77
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#define GPP_C10_IRQ 0x18
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#define GPP_C11_IRQ 0x19
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#define GPP_C12_IRQ 0x1A
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#define GPP_C13_IRQ 0x1B
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#define GPP_C14_IRQ 0x1C
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#define GPP_C15_IRQ 0x1D
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#define GPP_C16_IRQ 0x1E
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#define GPP_C17_IRQ 0x1F
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#define GPP_C18_IRQ 0x20
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#define GPP_C19_IRQ 0x21
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#define GPP_C20_IRQ 0x22
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#define GPP_C21_IRQ 0x23
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#define GPP_C22_IRQ 0x24
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#define GPP_C23_IRQ 0x25
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#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
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/* Group D */
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#define GPP_D0_IRQ 0x40
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#define GPP_D1_IRQ 0x41
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#define GPP_D2_IRQ 0x42
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#define GPP_D3_IRQ 0x43
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#define GPP_D4_IRQ 0x44
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#define GPP_D5_IRQ 0x45
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#define GPP_D6_IRQ 0x46
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#define GPP_D7_IRQ 0x47
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#define GPP_D8_IRQ 0x48
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#define GPP_D9_IRQ 0x49
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#define GPP_D10_IRQ 0x4A
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#define GPP_D11_IRQ 0x4B
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#define GPP_D12_IRQ 0x4C
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#define GPP_D13_IRQ 0x4D
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#define GPP_D14_IRQ 0x4E
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#define GPP_D15_IRQ 0x4F
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#define GPP_D16_IRQ 0x50
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#define GPP_D17_IRQ 0x51
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#define GPP_D18_IRQ 0x52
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#define GPP_D19_IRQ 0x53
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#else
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/* Group D */
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#define GPP_D0_IRQ 0x2C
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#define GPP_D1_IRQ 0x2D
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#define GPP_D2_IRQ 0x2E
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#define GPP_D3_IRQ 0x2F
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#define GPP_D4_IRQ 0x30
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#define GPP_D5_IRQ 0x31
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#define GPP_D6_IRQ 0x32
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#define GPP_D7_IRQ 0x33
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#define GPP_D8_IRQ 0x34
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#define GPP_D9_IRQ 0x35
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#define GPP_D10_IRQ 0x36
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#define GPP_D11_IRQ 0x37
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#define GPP_D12_IRQ 0x38
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#define GPP_D13_IRQ 0x39
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#define GPP_D14_IRQ 0x3A
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#define GPP_D15_IRQ 0x3B
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#define GPP_D16_IRQ 0x3C
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#define GPP_D17_IRQ 0x3D
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#define GPP_D18_IRQ 0x3E
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#define GPP_D19_IRQ 0x3F
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#endif
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/* Group E */
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#define GPP_E0_IRQ 0x26
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#define GPP_E1_IRQ 0x27
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#define GPP_E2_IRQ 0x28
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#define GPP_E3_IRQ 0x29
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#define GPP_E4_IRQ 0x30
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#define GPP_E5_IRQ 0x31
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#define GPP_E6_IRQ 0x32
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#define GPP_E7_IRQ 0x33
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#define GPP_E8_IRQ 0x34
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#define GPP_E9_IRQ 0x35
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#define GPP_E10_IRQ 0x36
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#define GPP_E11_IRQ 0x37
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#define GPP_E12_IRQ 0x38
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#define GPP_E13_IRQ 0x39
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#define GPP_E14_IRQ 0x3A
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#define GPP_E15_IRQ 0x3B
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#define GPP_E16_IRQ 0x3C
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#define GPP_E17_IRQ 0x3D
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#define GPP_E18_IRQ 0x3E
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#define GPP_E19_IRQ 0x3F
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#define GPP_E20_IRQ 0x40
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#define GPP_E21_IRQ 0x41
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#define GPP_E22_IRQ 0x42
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#define GPP_E23_IRQ 0x43
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/* Group F */
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#define GPP_F0_IRQ 0x56
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#define GPP_F1_IRQ 0x57
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#define GPP_F2_IRQ 0x58
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#define GPP_F3_IRQ 0x59
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#define GPP_F4_IRQ 0x5A
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#define GPP_F5_IRQ 0x5B
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#define GPP_F6_IRQ 0x5C
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#define GPP_F7_IRQ 0x5D
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#define GPP_F8_IRQ 0x5E
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#define GPP_F9_IRQ 0x5F
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#define GPP_F10_IRQ 0x60
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#define GPP_F11_IRQ 0x61
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#define GPP_F12_IRQ 0x62
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#define GPP_F13_IRQ 0x63
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#define GPP_F14_IRQ 0x64
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#define GPP_F15_IRQ 0x65
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#define GPP_F16_IRQ 0x66
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#define GPP_F17_IRQ 0x67
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#define GPP_F18_IRQ 0x68
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#define GPP_F19_IRQ 0x69
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#define GPP_F20_IRQ 0x6A
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#define GPP_F21_IRQ 0x6B
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#define GPP_F22_IRQ 0x6C
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#define GPP_F23_IRQ 0x6D
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#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
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/* Group H */
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#define GPP_H0_IRQ 0x28
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#define GPP_H1_IRQ 0x29
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#define GPP_H2_IRQ 0x2A
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#define GPP_H3_IRQ 0x2B
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#define GPP_H4_IRQ 0x2C
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#define GPP_H5_IRQ 0x2D
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#define GPP_H6_IRQ 0x2E
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#define GPP_H7_IRQ 0x2F
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#define GPP_H8_IRQ 0x30
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#define GPP_H9_IRQ 0x31
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#define GPP_H10_IRQ 0x32
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#define GPP_H11_IRQ 0x33
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#define GPP_H12_IRQ 0x34
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#define GPP_H13_IRQ 0x35
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#define GPP_H14_IRQ 0x36
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#define GPP_H15_IRQ 0x37
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#define GPP_H16_IRQ 0x38
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#define GPP_H17_IRQ 0x39
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#define GPP_H18_IRQ 0x3A
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#define GPP_H19_IRQ 0x3B
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#define GPP_H20_IRQ 0x3C
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#define GPP_H21_IRQ 0x3D
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#define GPP_H22_IRQ 0x3E
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#define GPP_H23_IRQ 0x3F
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/* Group I */
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#define GPP_I0_IRQ 0x74
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#define GPP_I1_IRQ 0x75
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#define GPP_I2_IRQ 0x76
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#define GPP_I3_IRQ 0x77
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#define GPP_I4_IRQ 0x18
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#define GPP_I5_IRQ 0x19
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#define GPP_I6_IRQ 0x1A
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#define GPP_I7_IRQ 0x1B
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#define GPP_I8_IRQ 0x1C
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#define GPP_I9_IRQ 0x1D
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#define GPP_I10_IRQ 0x1E
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#define GPP_I11_IRQ 0x1F
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#define GPP_I12_IRQ 0x20
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#define GPP_I13_IRQ 0x21
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#define GPP_I14_IRQ 0x22
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#define GPP_I15_IRQ 0x23
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#define GPP_I16_IRQ 0x24
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#define GPP_I17_IRQ 0x25
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#define GPP_I18_IRQ 0x26
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#define GPP_I19_IRQ 0x27
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#else
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/* Group H */
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#define GPP_H0_IRQ 0x74
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#define GPP_H1_IRQ 0x75
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#define GPP_H2_IRQ 0x76
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#define GPP_H3_IRQ 0x77
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#define GPP_H4_IRQ 0x18
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#define GPP_H5_IRQ 0x19
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#define GPP_H6_IRQ 0x1A
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#define GPP_H7_IRQ 0x1B
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#define GPP_H8_IRQ 0x1C
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#define GPP_H9_IRQ 0x1D
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#define GPP_H10_IRQ 0x1E
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#define GPP_H11_IRQ 0x1F
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#define GPP_H12_IRQ 0x20
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#define GPP_H13_IRQ 0x21
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#define GPP_H14_IRQ 0x22
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#define GPP_H15_IRQ 0x23
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#define GPP_H16_IRQ 0x24
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#define GPP_H17_IRQ 0x25
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#define GPP_H18_IRQ 0x26
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#define GPP_H19_IRQ 0x27
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#define GPP_H20_IRQ 0x28
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#define GPP_H21_IRQ 0x29
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#define GPP_H22_IRQ 0x2A
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#define GPP_H23_IRQ 0x2B
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#endif
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/* Group R */
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#define GPP_R0_IRQ 0x58
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#define GPP_R1_IRQ 0x59
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#define GPP_R2_IRQ 0x5A
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#define GPP_R3_IRQ 0x5B
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#define GPP_R4_IRQ 0x5C
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#define GPP_R5_IRQ 0x5D
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#define GPP_R6_IRQ 0x5E
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#define GPP_R7_IRQ 0x5F
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/* Group S */
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#define GPP_S0_IRQ 0x6C
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#define GPP_S1_IRQ 0x6D
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#define GPP_S2_IRQ 0x6E
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#define GPP_S3_IRQ 0x6F
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#define GPP_S4_IRQ 0x70
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#define GPP_S5_IRQ 0x71
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#define GPP_S6_IRQ 0x72
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#define GPP_S7_IRQ 0x73
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/* Group GPD */
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#define GPD0_IRQ 0x60
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#define GPD1_IRQ 0x61
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#define GPD2_IRQ 0x62
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#define GPD3_IRQ 0x63
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#define GPD4_IRQ 0x64
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#define GPD5_IRQ 0x65
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#define GPD6_IRQ 0x66
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#define GPD7_IRQ 0x67
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#define GPD8_IRQ 0x68
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#define GPD9_IRQ 0x69
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#define GPD10_IRQ 0x6A
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#define GPD11_IRQ 0x6B
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/* Register defines. */
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#define GPIO_MISCCFG 0x10
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#define GPE_DW_SHIFT 8
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#define GPE_DW_MASK 0xfff00
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#define HOSTSW_OWN_REG_0 0xb0
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#define GPI_INT_STS_0 0x100
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#define GPI_INT_EN_0 0x110
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#define GPI_SMI_STS_0 0x180
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#define GPI_SMI_EN_0 0x1A0
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#define PAD_CFG_BASE 0x700
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#endif
stddef.h
src
soc
intel
alderlake
include
soc
gpio_defs.h
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