coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
irqroute.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <soc/irq.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#define PCI_DEV_PIRQ_ROUTES \
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PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \
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PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(MMC45_DEV, D, E, F, G), \
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PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \
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PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D)
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#define PIRQ_PIC_ROUTES \
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PIRQ_PIC(A, DISABLE), \
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PIRQ_PIC(B, DISABLE), \
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PIRQ_PIC(C, DISABLE), \
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PIRQ_PIC(D, DISABLE), \
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PIRQ_PIC(E, DISABLE), \
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PIRQ_PIC(F, DISABLE), \
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PIRQ_PIC(G, DISABLE), \
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PIRQ_PIC(H, DISABLE)
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/* CORE bank DIRQs - up to 16 supported */
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#define TPAD_IRQ_OFFSET 0
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#define TOUCH_IRQ_OFFSET 1
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#define I8042_IRQ_OFFSET 2
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#define ALS_IRQ_OFFSET 3
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/* Corresponding SCORE GPIO pins */
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#define TPAD_IRQ_GPIO 55
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#define TOUCH_IRQ_GPIO 72
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#define I8042_IRQ_GPIO 101
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#define ALS_IRQ_GPIO 70
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/* SUS bank DIRQs - up to 16 supported */
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#define CODEC_IRQ_OFFSET 0
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/* Corresponding SUS GPIO pins */
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#define CODEC_IRQ_GPIO 9
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irqroute.h
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