coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
w83627dhg.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #ifndef SUPERIO_WINBOND_W83627DHG_H
4 #define SUPERIO_WINBOND_W83627DHG_H
5 
6 #include <device/pnp_type.h>
7 
8 #define W83627DHG_FDC 0 /* Floppy */
9 #define W83627DHG_PP 1 /* Parallel port */
10 #define W83627DHG_SP1 2 /* Com1 */
11 #define W83627DHG_SP2 3 /* Com2 */
12 #define W83627DHG_KBC 5 /* PS/2 keyboard & mouse */
13 #define W83627DHG_SPI 6 /* Serial peripheral interface */
14 #define W83627DHG_WDTO_PLED 8 /* WDTO#, PLED */
15 #define W83627DHG_ACPI 10 /* ACPI */
16 #define W83627DHG_HWM 11 /* Hardware monitor */
17 #define W83627DHG_PECI_SST 12 /* PECI, SST */
18 
19 /* The following are handled using "virtual LDNs" (hence the _V suffix). */
20 #define W83627DHG_GPIO6_V 7 /* GPIO6 */
21 #define W83627DHG_GPIO2345_V 9 /* GPIO2, GPIO3, GPIO4, GPIO5 */
22 
23 /*
24  * Virtual devices sharing the enables are encoded as follows:
25  * VLDN = baseLDN[7:0] | [10:8] bitpos of enable in 0x30 of baseLDN
26  */
27 
28 /* GPIO6 has bit 3 as enable (instead of bit 0 as usual). */
29 #define W83627DHG_GPIO6 ((3 << 8) | W83627DHG_GPIO6_V)
30 
31 #define W83627DHG_GPIO2 ((0 << 8) | W83627DHG_GPIO2345_V)
32 #define W83627DHG_GPIO3 ((1 << 8) | W83627DHG_GPIO2345_V)
33 #define W83627DHG_GPIO4 ((2 << 8) | W83627DHG_GPIO2345_V)
34 #define W83627DHG_GPIO5 ((3 << 8) | W83627DHG_GPIO2345_V)
35 
36 /* Note: There is no GPIO1 on the W83627DHG as per datasheet. */
37 
42 
43 #endif /* SUPERIO_WINBOND_W83627DHG_H */
u32 pnp_devfn_t
Definition: pnp_type.h:8
void w83627dhg_set_clksel_48(pnp_devfn_t dev)
Definition: early_serial.c:40
void pnp_exit_ext_func_mode(pnp_devfn_t dev)
Definition: early_serial.c:17
void pnp_enter_ext_func_mode(pnp_devfn_t dev)
Definition: early_serial.c:11
void w83627dhg_enable_i2c(pnp_devfn_t dev)
Select Pin 89, Pin 90 function as I2C interface SDA, SCL.
Definition: early_serial.c:26