coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
onboard.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef ONBOARD_H
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#define ONBOARD_H
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#include <
mainboard/google/cyan/irqroute.h
>
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/*
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* Calculation of gpio based irq.
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* Gpio banks ordering : GPSW, GPNC, GPEC, GPSE
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* Max direct irq (MAX_DIRECT_IRQ) is 114.
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* Size of gpio banks are
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* GPSW_SIZE = 98
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* GPNC_SIZE = 73
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* GPEC_SIZE = 27
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* GPSE_SIZE = 86
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*/
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/* KBD: Gpio index in N bank */
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#define BOARD_I8042_GPIO_INDEX 17
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/* Audio: Gpio index in SW bank */
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#define JACK_DETECT_GPIO_INDEX 95
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/* SCI: Gpio index in N bank */
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#define BOARD_SCI_GPIO_INDEX 15
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/* Trackpad: Gpio index in N bank */
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#define BOARD_TRACKPAD_GPIO_INDEX 18
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/* Touch: Gpio index in N bank */
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#define BOARD_TOUCH_GPIO_INDEX 19
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#define BOARD_TRACKPAD_NAME "trackpad"
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#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1)
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#define BOARD_TRACKPAD_I2C_BUS 5
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#define BOARD_TRACKPAD_I2C_ADDR 0x15
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#define BOARD_TOUCHSCREEN_NAME "touchscreen"
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#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2)
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#define BOARD_TOUCHSCREEN_I2C_BUS 0
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#define BOARD_TOUCHSCREEN_I2C_ADDR 0x10
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/* SD CARD gpio */
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#define SDCARD_CD 81
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#define AUDIO_CODEC_HID "10EC5650"
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#define AUDIO_CODEC_CID "10EC5650"
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#define AUDIO_CODEC_DDN "RTEK Codec Controller"
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#define AUDIO_CODEC_I2C_ADDR 0x1A
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/* I2C data hold time */
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#define BOARD_I2C1_DATA_HOLD_TIME 0x28
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#define BOARD_I2C6_DATA_HOLD_TIME 0x28
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#define DPTF_CPU_PASSIVE 80
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#define DPTF_CPU_CRITICAL 90
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#endif
irqroute.h
src
mainboard
google
cyan
variants
kefka
include
variant
onboard.h
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