coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
vpd.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #ifndef DELTALAKE_VPD_H
4 #define DELTALAKE_VPD_H
5 
6 /* VPD variable for enabling/disabling FRB2 timer. 1/0: Enable/disable */
7 #define FRB2_TIMER "frb2_timer_enable"
8 #define FRB2_TIMER_DEFAULT 1 /* Default value when the VPD variable is not found */
9 
10 /* VPD variable for setting FRB2 timer countdown value. */
11 #define FRB2_COUNTDOWN "frb2_countdown"
12 /* Default countdown is 15 minutes when the VPD variable is not found */
13 #define FRB2_COUNTDOWN_DEFAULT 9000
14 
15 /* VPD variable for setting FRB2 timer action.
16  0: No action, 1: hard reset, 2: power down, 3: power cycle */
17 #define FRB2_ACTION "frb2_action"
18 #define FRB2_ACTION_DEFAULT 0 /* Default no action when the VPD variable is not found */
19 
20 /* Define the VPD keys for UPD variables that can be overwritten */
21 #define FSP_LOG "fsp_log_enable" /* 1 or 0: enable or disable FSP SOL log */
22 #define FSP_LOG_DEFAULT 1 /* Default value when the VPD variable is not found */
23 
24 /* FSP debug print level: 1:Fatal, 2:Warning, 4:Summary, 8:Detail, 0x0F:All */
25 #define FSP_LOG_LEVEL "fsp_log_level"
26 #define FSP_LOG_LEVEL_DEFAULT 8 /* Default value when the VPD variable is not found */
27 
28 /* DCI enable */
29 #define FSP_DCI "fsp_dci_enable" /* 1 or 0: enable or disable DCI */
30 #define FSP_DCI_DEFAULT 0 /* Default value when the VPD variable is not found */
31 
32 /* coreboot log level */
33 #define COREBOOT_LOG_LEVEL "coreboot_log_level"
34 #define COREBOOT_LOG_LEVEL_DEFAULT 4
35 
36 /* FSPM MemRefreshWatermark: 0:Auto, 1: high(default), 2: low */
37 #define FSPM_MEMREFRESHWATERMARK "fspm_mem_refresh_watermark"
38 #define FSPM_MEMREFRESHWATERMARK_DEFAULT 1
39 
40 /* coreboot uart io select: 0 = 0x3f8, 1 = 0x2f8, 2 = 0x3e8, 3 = 0x2e8 */
41 #define COREBOOT_UART_IO "coreboot_uart_io"
42 #define COREBOOT_UART_IO_DEFAULT 1
43 
44 /* FSP dimm frequency limit, 0:Auto, 1:DDR_1333, 2:DDR_1600, 3:DDR_1866, 4:DDR_2133,
45  * 5:DDR_2400, 6:DDR_2666, 7:DDR_2933, 8:DDR_3200 */
46 #define FSP_DIMM_FREQ "fsp_dimm_freq"
47 #define FSP_DIMM_FREQ_DEFAULT 0
48 
49 /* Skip TXT lockdown */
50 #define SKIP_INTEL_TXT_LOCKDOWN "skip_intel_txt_lockdown"
51 #define SKIP_INTEL_TXT_LOCKDOWN_DEFAULT 0
52 
53 /* Force memory training: 0 = Disable, 1 = Enable, Default setting is 0 */
54 #define MEM_TRAIN_FORCE "mem_train_force_enable"
55 
56 #endif