coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
usb.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef _SOC_USB_H_
4 #define _SOC_USB_H_
5 
6 #include <stdint.h>
7 
8 #define USB2_EMP_OFF 0
9 #define USB2_DE_EMP_ON 1
10 #define USB2_PRE_EMP_ON 2
11 
12 #define USB2_FULL_BIT_PRE_EMP 0
13 #define USB2_HALF_BIT_PRE_EMP 1
14 
15 #define USB2_BIAS_0MV 0
16 #define USB2_BIAS_11MV 1
17 #define USB2_BIAS_17MV 2
18 #define USB2_BIAS_28MV 3
19 #define USB2_BIAS_28MV2 4
20 #define USB2_BIAS_39MV 5
21 #define USB2_BIAS_45MV 6
22 #define USB2_BIAS_56MV 7
23 
24 struct usb2_port_config {
26  uint8_t ocpin;
31 };
32 
33 /* USB Overcurrent pins definition */
34 enum {
35  OC0,
36  OC1,
37  OC2,
38  OC3,
39  OC4,
40  OC5,
41  OC_SKIP = 8, /* Skip OC programming */
42 };
43 
44 #define USB2_PORT_EMPTY { \
45  .enable = 0, \
46  .ocpin = OC_SKIP, \
47  .tx_bias = USB2_BIAS_0MV, \
48  .tx_emp_enable = USB2_EMP_OFF, \
49  .pre_emp_bias = USB2_BIAS_0MV, \
50  .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
51 }
52 
53 /*
54  * Standard USB Port based on length:
55  * - External
56  * - Back Panel
57  * - OTG
58  * - M.2
59  * - Internal device down
60  */
61 
62 /* Max TX and Pre-emp settings */
63 #define USB2_PORT_MAX(pin) { \
64  .enable = 1, \
65  .ocpin = pin, \
66  .tx_bias = USB2_BIAS_56MV, \
67  .tx_emp_enable = USB2_PRE_EMP_ON, \
68  .pre_emp_bias = USB2_BIAS_56MV, \
69  .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
70 }
71 
72 /* 11.5"-12" */
73 #define USB2_PORT_LONG(pin) { \
74  .enable = 1, \
75  .ocpin = pin, \
76  .tx_bias = USB2_BIAS_39MV, \
77  .tx_emp_enable = USB2_PRE_EMP_ON, \
78  .pre_emp_bias = USB2_BIAS_56MV, \
79  .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
80 }
81 
82 /* 6"-11.5" */
83 #define USB2_PORT_MID(pin) { \
84  .enable = 1, \
85  .ocpin = pin, \
86  .tx_bias = USB2_BIAS_0MV, \
87  .tx_emp_enable = USB2_PRE_EMP_ON, \
88  .pre_emp_bias = USB2_BIAS_56MV, \
89  .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
90 }
91 
92 /* 3"-6" */
93 #define USB2_PORT_SHORT(pin) { \
94  .enable = 1, \
95  .ocpin = pin, \
96  .tx_bias = USB2_BIAS_39MV, \
97  .tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \
98  .pre_emp_bias = USB2_BIAS_39MV, \
99  .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \
100 }
101 
102 /* Type-C Port, no BC1.2 charge detect module / MUX */
103 #define USB2_PORT_TYPE_C(pin) { \
104  .enable = 1, \
105  .ocpin = pin, \
106  .tx_bias = USB2_BIAS_0MV, \
107  .tx_emp_enable = USB2_PRE_EMP_ON, \
108  .pre_emp_bias = USB2_BIAS_56MV, \
109  .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
110 }
111 
112 /* Port with BC1.2 charge detect module / MUX */
113 #define USB2_PORT_BC12_MUX(pin) { \
114  .enable = 1, \
115  .ocpin = pin, \
116  .tx_bias = USB2_BIAS_0MV, \
117  .tx_emp_enable = USB2_PRE_EMP_ON, \
118  .pre_emp_bias = USB2_BIAS_56MV, \
119  .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
120 }
121 
122 /* Internal Flex Cable, 3"-5" + cable + 2" card */
123 #define USB2_PORT_FLEX(pin) { \
124  .enable = 1, \
125  .ocpin = pin, \
126  .tx_bias = USB2_BIAS_0MV, \
127  .tx_emp_enable = USB2_PRE_EMP_ON, \
128  .pre_emp_bias = USB2_BIAS_56MV, \
129  .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
130 }
131 
132 /* Docking, 3"-9" */
133 #define USB2_PORT_DOCKING_LONG(pin) { \
134  .enable = 1, \
135  .ocpin = pin, \
136  .tx_bias = USB2_BIAS_0MV, \
137  .tx_emp_enable = USB2_PRE_EMP_ON, \
138  .pre_emp_bias = USB2_BIAS_56MV, \
139  .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
140 }
141 
142 /* Docking, 3"-6" */
143 #define USB2_PORT_DOCKING_SHORT(pin) { \
144  .enable = 1, \
145  .ocpin = pin, \
146  .tx_bias = USB2_BIAS_17MV, \
147  .tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \
148  .pre_emp_bias = USB2_BIAS_45MV, \
149  .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \
150 }
151 
152 /* 2:1 Detachable, 2"-4" on tablet + 2"-4" on base */
153 #define USB2_PORT_DETACHABLE_TABLET(pin) { \
154  .enable = 1, \
155  .ocpin = pin, \
156  .tx_bias = USB2_BIAS_56MV, \
157  .tx_emp_enable = USB2_PRE_EMP_ON, \
158  .pre_emp_bias = USB2_BIAS_56MV, \
159  .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
160 }
161 
162 struct usb3_port_config {
163  uint8_t enable;
164  uint8_t ocpin;
167 };
168 
169 #define USB3_PORT_EMPTY { \
170  .enable = 0, \
171  .ocpin = OC_SKIP, \
172  .tx_de_emp = 0x00, \
173  .tx_downscale_amp = 0x00, \
174 }
175 
176 #define USB3_PORT_DEFAULT(pin) { \
177  .enable = 1, \
178  .ocpin = pin, \
179  .tx_de_emp = 0x29, \
180  .tx_downscale_amp = 0x00, \
181 }
182 
183 /*
184  * Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds
185  * to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to
186  * decide what ports need to set PORTSCN/PORTSCXUSB3 register bits.
187  */
188 #define USB_PORT_WAKE_ENABLE(x) (1 << ((x) - 1))
189 
190 #endif
@ OC2
Definition: usb.h:41
@ OC3
Definition: usb.h:42
@ OC5
Definition: usb.h:44
@ OC0
Definition: usb.h:39
@ OC_SKIP
Definition: usb.h:48
@ OC1
Definition: usb.h:40
@ OC4
Definition: usb.h:43
unsigned char uint8_t
Definition: stdint.h:8
uint8_t tx_bias
Definition: usb.h:30
uint8_t ocpin
Definition: usb.h:29
uint8_t pre_emp_bias
Definition: usb.h:32
uint8_t enable
Definition: usb.h:28
uint8_t pre_emp_bit
Definition: usb.h:33
uint8_t tx_emp_enable
Definition: usb.h:31
uint8_t ocpin
Definition: usb.h:132
uint8_t tx_downscale_amp
Definition: usb.h:134
uint8_t tx_de_emp
Definition: usb.h:133
uint8_t enable
Definition: usb.h:131