coreboot
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i23c_pad_def.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef AMD_BLOCK_I23C_PAD_DEF_H
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#define AMD_BLOCK_I23C_PAD_DEF_H
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#include <types.h>
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/* MISC_I2Cx_PAD_CTRL and MISC_I23Cx_PAD_CTRL are in the same place, but have different bit
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definitions. Which one is present depends on the SoC. */
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#define MISC_I23C0_PAD_CTRL 0xd8
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#define MISC_I23C_PAD_CTRL(bus) (MISC_I23C0_PAD_CTRL + 4 * (bus))
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#define I23C_PAD_CTRL_OD_RP_SW_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
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#define I23C_PAD_CTRL_OD_RP_SW_SHIFT 0
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#define I23C_PAD_CTRL_RX_SEL_MASK (BIT(4) | BIT(5))
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#define I23C_PAD_CTRL_RX_SHIFT 4
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#define I23C_PAD_CTRL_RX_SEL_OFF (0 << I23C_PAD_CTRL_RX_SHIFT)
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#define I23C_PAD_CTRL_RX_SEL_ON (3 << I23C_PAD_CTRL_RX_SHIFT)
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#define I23C_PAD_CTRL_SLEW_N_MASK (BIT(6) | BIT(7))
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#define I23C_PAD_CTRL_SLEW_N_SHIFT 6
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#define I23C_PAD_CTRL_SLEW_N_DIS (0 << I23C_PAD_CTRL_SLEW_N_SHIFT)
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#define I23C_PAD_CTRL_SLEW_N_FAST (3 << I23C_PAD_CTRL_SLEW_N_SHIFT)
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#define I23C_PAD_CTRL_FALLSLEW_SEL_MASK (BIT(8) | BIT(9))
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#define I23C_PAD_CTRL_FALLSLEW_SEL_SHIFT 8
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#define I23C_PAD_CTRL_FALLSLEW_SEL_STD (0 << I23C_PAD_CTRL_FALLSLEW_SEL_SHIFT)
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#define I23C_PAD_CTRL_FALLSLEW_SEL_LOW (3 << I23C_PAD_CTRL_FALLSLEW_SEL_SHIFT)
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#define I23C_PAD_CTRL_SPIKE_RC_EN_MASK (BIT(10) | BIT(11))
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#define I23C_PAD_CTRL_SPIKE_RC_EN_SHIFT 10
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#define I23C_PAD_CTRL_SPIKE_RC_DIS (0 << I23C_PAD_CTRL_SPIKE_RC_EN_SHIFT)
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#define I23C_PAD_CTRL_SPIKE_RC_EN (3 << I23C_PAD_CTRL_SPIKE_RC_EN_SHIFT)
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#define I23C_PAD_CTRL_CAP_DOWN BIT(12)
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#define I23C_PAD_CTRL_CAP_UP BIT(13)
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#define I23C_PAD_CTRL_RES_DOWN BIT(14)
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#define I23C_PAD_CTRL_RES_UP BIT(15)
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#define I23C_PAD_CTRL_BIAS_CRT_EN_MASK (BIT(16) | BIT(17))
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#define I23C_PAD_CTRL_BIAS_CRT_EN_SHIFT 16
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#define I23C_PAD_CTRL_BIAS_CRT_DIS (0 << I23C_PAD_CTRL_BIAS_CRT_EN_SHIFT)
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#define I23C_PAD_CTRL_BIAS_CRT_EN (3 << I23C_PAD_CTRL_BIAS_CRT_EN_SHIFT)
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#define I23C_PAD_CTRL_SPARE0 BIT(18)
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#define I23C_PAD_CTRL_SPARE1 BIT(19)
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#define I23C_PAD_CTRL_COMP_SEL0 BIT(20)
/* unused */
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#define I23C_PAD_CTRL_COMP_SEL1 BIT(21)
/* unused */
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#define I23C_PAD_CTRL_RES_BIAS_EN_MASK (BIT(22) | BIT(23))
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#define I23C_PAD_CTRL_RES_BIAS_EN_SHIFT 22
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#define I23C_PAD_CTRL_RES_BIAS_T_COMP (0 << I23C_PAD_CTRL_RES_BIAS_EN_SHIFT)
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#define I23C_PAD_CTRL_RES_BIAS_CONST_GM (3 << I23C_PAD_CTRL_RES_BIAS_EN_SHIFT)
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#define I23C_PAD_CTRL_SLEW_P_MASK (BIT(24) | BIT(25))
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#define I23C_PAD_CTRL_SLEW_P_SHIFT 24
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#define I23C_PAD_CTRL_SLEW_P_DIS (0 << I23C_PAD_CTRL_SLEW_P_SHIFT)
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#define I23C_PAD_CTRL_SLEW_P_EN (3 << I23C_PAD_CTRL_SLEW_P_SHIFT)
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#define I23C_PAD_CTRL_MODE_I3C_I2C_MASK (BIT(26) | BIT(27))
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#define I23C_PAD_CTRL_MODE_I3C_I2C_SHIFT 26
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#define I23C_PAD_CTRL_MODE_I2C (0 << I23C_PAD_CTRL_MODE_I3C_I2C_SHIFT)
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#define I23C_PAD_CTRL_MODE_I3C (3 << I23C_PAD_CTRL_MODE_I3C_I2C_SHIFT)
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#define I23C_PAD_CTRL_MODE_1_8V_1_1V_MASK (BIT(28) | BIT(29))
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#define I23C_PAD_CTRL_MODE_1_8V_1_1V_SHIFT 28
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#define I23C_PAD_CTRL_MODE_1_1V (0 << I23C_PAD_CTRL_MODE_1_8V_1_1V_SHIFT)
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#define I23C_PAD_CTRL_MODE_1_8V (3 << I23C_PAD_CTRL_MODE_1_8V_1_1V_SHIFT)
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#define I23C_PAD_CTRL_SPIKE_C_SEL_MASK (BIT(30) | BIT(31))
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#define I23C_PAD_CTRL_SPIKE_C_SEL_SHIFT 30
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#define I23C_PAD_CTRL_SPIKE_C_SEL_DIS (0 << I23C_PAD_CTRL_SPIKE_C_SEL_SHIFT)
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#define I23C_PAD_CTRL_SPIKE_C_SEL_EN (3 << I23C_PAD_CTRL_SPIKE_C_SEL_SHIFT)
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#endif
/* AMD_BLOCK_I23C_PAD_DEF_H */
src
soc
amd
common
block
i2c
i23c_pad_def.h
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