coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
iomap.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef AMD_SABRINA_IOMAP_H
4 #define AMD_SABRINA_IOMAP_H
5 
6 #define I2C_MASTER_DEV_COUNT 4
7 #define I2C_MASTER_START_INDEX 0
8 #define I2C_PERIPHERAL_DEV_COUNT 0 /* TODO: Only master for now. */
9 #define I2C_CTRLR_COUNT (I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT)
10 
11 #if ENV_X86
12 
13 /* MMIO Ranges */
14 /* IO_APIC_ADDR defined in arch/x86 0xfec00000 */
15 #define GNB_IO_APIC_ADDR 0xfec01000
16 #define SPI_BASE_ADDRESS 0xfec10000
17 
18 /* FCH AL2AHB Registers */
19 #define ALINK_AHB_ADDRESS 0xfedc0000
20 
21 #define APU_I2C0_BASE 0xfedc2000
22 #define APU_I2C1_BASE 0xfedc3000
23 #define APU_I2C2_BASE 0xfedc4000
24 #define APU_I2C3_BASE 0xfedc5000
25 
26 #define APU_DMAC0_BASE 0xfedc7000
27 #define APU_DMAC1_BASE 0xfedc8000
28 #define APU_UART0_BASE 0xfedc9000
29 #define APU_UART1_BASE 0xfedca000
30 #define APU_DMAC2_BASE 0xfedcc000
31 #define APU_DMAC3_BASE 0xfedcd000
32 #define APU_UART2_BASE 0xfedce000
33 #define APU_UART3_BASE 0xfedcf000
34 #define APU_DMAC4_BASE 0xfedd0000
35 #define APU_UART4_BASE 0xfedd1000
36 
37 #define APU_EMMC_BASE 0xfedd5000
38 #define APU_EMMC_CONFIG_BASE 0xfedd5800
39 
40 #endif /* ENV_X86 */
41 
42 #define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1)
43 
44 /* I/O Ranges */
45 #define ACPI_IO_BASE 0x0400
46 #define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00)
47 #define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00)
48 #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02)
49 #define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04)
50 #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08)
51 #define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10)
52 #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20)
53 #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00)
54 #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04)
55 #define SMB_BASE_ADDR 0x0b00
56 
57 #endif /* AMD_SABRINA_IOMAP_H */