coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio_defs.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef _SOC_TIGERLAKE_GPIO_DEFS_H_
4 #define _SOC_TIGERLAKE_GPIO_DEFS_H_
5 
6 #ifndef __ACPI__
7 #include <stddef.h>
8 #endif
9 #include <soc/gpio_soc_defs.h>
10 
11 #define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */
12 
13 #define NUM_GPIO_COMx_GPI_REGS(n) \
14  (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
15 
16 #define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS)
17 #define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS)
18 #define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS)
19 #define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS)
20 #define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS)
21 
22 #define NUM_GPI_STATUS_REGS \
23  ((NUM_GPIO_COM0_GPI_REGS) +\
24  (NUM_GPIO_COM1_GPI_REGS) +\
25  (NUM_GPIO_COM2_GPI_REGS) +\
26  (NUM_GPIO_COM4_GPI_REGS) +\
27  (NUM_GPIO_COM5_GPI_REGS))
28 /*
29  * IOxAPIC IRQs for the GPIOs
30  */
31 
32 /* Group B */
33 #define GPP_B0_IRQ 0x18
34 #define GPP_B1_IRQ 0x19
35 #define GPP_B2_IRQ 0x1A
36 #define GPP_B3_IRQ 0x1B
37 #define GPP_B4_IRQ 0x1C
38 #define GPP_B5_IRQ 0x1D
39 #define GPP_B6_IRQ 0x1E
40 #define GPP_B7_IRQ 0x1F
41 #define GPP_B8_IRQ 0x20
42 #define GPP_B9_IRQ 0x21
43 #define GPP_B10_IRQ 0x22
44 #define GPP_B11_IRQ 0x23
45 #define GPP_B12_IRQ 0x24
46 #define GPP_B13_IRQ 0x25
47 #define GPP_B14_IRQ 0x26
48 #define GPP_B15_IRQ 0x27
49 #define GPP_B16_IRQ 0x28
50 #define GPP_B17_IRQ 0x29
51 #define GPP_B18_IRQ 0x2A
52 #define GPP_B19_IRQ 0x2B
53 #define GPP_B20_IRQ 0x2C
54 #define GPP_B21_IRQ 0x2D
55 #define GPP_B22_IRQ 0x2E
56 #define GPP_B23_IRQ 0x2F
57 
58 /* Group T */
59 #define GPP_T0_IRQ 0x30
60 #define GPP_T1_IRQ 0x31
61 #define GPP_T2_IRQ 0x32
62 #define GPP_T3_IRQ 0x33
63 #define GPP_T4_IRQ 0x34
64 #define GPP_T5_IRQ 0x35
65 #define GPP_T6_IRQ 0x36
66 #define GPP_T7_IRQ 0x37
67 #define GPP_T8_IRQ 0x38
68 #define GPP_T9_IRQ 0x39
69 #define GPP_T10_IRQ 0x3A
70 #define GPP_T11IRQ 0x3B
71 #define GPP_T12_IRQ 0x3C
72 #define GPP_T13_IRQ 0x3D
73 #define GPP_T14_IRQ 0x3E
74 #define GPP_T15_IRQ 0x3F
75 
76 /* Group A */
77 #define GPP_A0_IRQ 0x40
78 #define GPP_A1_IRQ 0x41
79 #define GPP_A2_IRQ 0x42
80 #define GPP_A3_IRQ 0x43
81 #define GPP_A4_IRQ 0x44
82 #define GPP_A5_IRQ 0x45
83 #define GPP_A6_IRQ 0x46
84 #define GPP_A7_IRQ 0x47
85 #define GPP_A8_IRQ 0x48
86 #define GPP_A9_IRQ 0x49
87 #define GPP_A10_IRQ 0x4A
88 #define GPP_A11_IRQ 0x4B
89 #define GPP_A12_IRQ 0x4C
90 #define GPP_A13_IRQ 0x4D
91 #define GPP_A14_IRQ 0x4E
92 #define GPP_A15_IRQ 0x4F
93 #define GPP_A16_IRQ 0x50
94 #define GPP_A17_IRQ 0x51
95 #define GPP_A18_IRQ 0x52
96 #define GPP_A19_IRQ 0x53
97 #define GPP_A20_IRQ 0x54
98 #define GPP_A21_IRQ 0x55
99 #define GPP_A22_IRQ 0x56
100 #define GPP_A23_IRQ 0x57
101 
102 /* Group R */
103 #define GPP_R0_IRQ 0x58
104 #define GPP_R1_IRQ 0x59
105 #define GPP_R2_IRQ 0x5A
106 #define GPP_R3_IRQ 0x5B
107 #define GPP_R4_IRQ 0x5C
108 #define GPP_R5_IRQ 0x5D
109 #define GPP_R6_IRQ 0x5E
110 #define GPP_R7_IRQ 0x5F
111 
112 /* Group D */
113 #define GPD0_IRQ 0x60
114 #define GPD1_IRQ 0x61
115 #define GPD2_IRQ 0x62
116 #define GPD3_IRQ 0x63
117 #define GPD4_IRQ 0x64
118 #define GPD5_IRQ 0x65
119 #define GPD6_IRQ 0x66
120 #define GPD7_IRQ 0x67
121 #define GPD8_IRQ 0x68
122 #define GPD9_IRQ 0x69
123 #define GPD10_IRQ 0x6A
124 #define GPD11_IRQ 0x6B
125 
126 /* Group S */
127 #define GPP_S0_IRQ 0x6C
128 #define GPP_S1_IRQ 0x6D
129 #define GPP_S2_IRQ 0x6E
130 #define GPP_S3_IRQ 0x6F
131 #define GPP_S4_IRQ 0x70
132 #define GPP_S5_IRQ 0x71
133 #define GPP_S6_IRQ 0x72
134 #define GPP_S7_IRQ 0x73
135 
136 /* Group H */
137 #define GPP_H0_IRQ 0x74
138 #define GPP_H1_IRQ 0x75
139 #define GPP_H2_IRQ 0x76
140 #define GPP_H3_IRQ 0x77
141 #define GPP_H4_IRQ 0x18
142 #define GPP_H5_IRQ 0x19
143 #define GPP_H6_IRQ 0x1A
144 #define GPP_H7_IRQ 0x1B
145 #define GPP_H8_IRQ 0x1C
146 #define GPP_H9_IRQ 0x1D
147 #define GPP_H10_IRQ 0x1E
148 #define GPP_H11_IRQ 0x1F
149 #define GPP_H12_IRQ 0x20
150 #define GPP_H13_IRQ 0x21
151 #define GPP_H14_IRQ 0x22
152 #define GPP_H15_IRQ 0x23
153 #define GPP_H16_IRQ 0x24
154 #define GPP_H17_IRQ 0x25
155 #define GPP_H18_IRQ 0x26
156 #define GPP_H19_IRQ 0x27
157 #define GPP_H20_IRQ 0x28
158 #define GPP_H21_IRQ 0x29
159 #define GPP_H22_IRQ 0x2A
160 #define GPP_H23_IRQ 0x2B
161 
162 /* Group D */
163 #define GPP_D0_IRQ 0x2C
164 #define GPP_D1_IRQ 0x2D
165 #define GPP_D2_IRQ 0x2E
166 #define GPP_D3_IRQ 0x2F
167 #define GPP_D4_IRQ 0x30
168 #define GPP_D5_IRQ 0x31
169 #define GPP_D6_IRQ 0x32
170 #define GPP_D7_IRQ 0x33
171 #define GPP_D8_IRQ 0x34
172 #define GPP_D9_IRQ 0x35
173 #define GPP_D10_IRQ 0x36
174 #define GPP_D11_IRQ 0x37
175 #define GPP_D12_IRQ 0x38
176 #define GPP_D13_IRQ 0x39
177 #define GPP_D14_IRQ 0x3A
178 #define GPP_D15_IRQ 0x3B
179 #define GPP_D16_IRQ 0x3C
180 #define GPP_D17_IRQ 0x3D
181 #define GPP_D18_IRQ 0x3E
182 #define GPP_D19_IRQ 0x3F
183 
184 /* Group U */
185 #define GPP_U0_IRQ 0x40
186 #define GPP_U1IRQ 0x41
187 #define GPP_U2_IRQ 0x42
188 #define GPP_U3_IRQ 0x43
189 #define GPP_U4_IRQ 0x44
190 #define GPP_U5_IRQ 0x45
191 #define GPP_U6_IRQ 0x46
192 #define GPP_U7_IRQ 0x47
193 #define GPP_U8_IRQ 0x48
194 #define GPP_U9_IRQ 0x49
195 #define GPP_U10_IRQ 0x4A
196 #define GPP_U11_IRQ 0x4B
197 #define GPP_U12_IRQ 0x4C
198 #define GPP_U13_IRQ 0x4D
199 #define GPP_U14_IRQ 0x4E
200 #define GPP_U15_IRQ 0x4F
201 #define GPP_U16_IRQ 0x50
202 #define GPP_U17_IRQ 0x51
203 #define GPP_U18_IRQ 0x52
204 #define GPP_U19_IRQ 0x53
205 
206 #define GPP_VGPIO4_IRQ 0x54
207 
208 /* Group F */
209 #define GPP_F0_IRQ 0x56
210 #define GPP_F1_IRQ 0x57
211 #define GPP_F2_IRQ 0x58
212 #define GPP_F3_IRQ 0x59
213 #define GPP_F4_IRQ 0x5A
214 #define GPP_F5_IRQ 0x5B
215 #define GPP_F6_IRQ 0x5C
216 #define GPP_F7_IRQ 0x5D
217 #define GPP_F8_IRQ 0x5E
218 #define GPP_F9_IRQ 0x5F
219 #define GPP_F10_IRQ 0x60
220 #define GPP_F11_IRQ 0x61
221 #define GPP_F12_IRQ 0x62
222 #define GPP_F13_IRQ 0x63
223 #define GPP_F14_IRQ 0x64
224 #define GPP_F15_IRQ 0x65
225 #define GPP_F16_IRQ 0x66
226 #define GPP_F17_IRQ 0x67
227 #define GPP_F18_IRQ 0x68
228 #define GPP_F19_IRQ 0x69
229 #define GPP_F20_IRQ 0x6A
230 #define GPP_F21_IRQ 0x6B
231 #define GPP_F22_IRQ 0x6C
232 #define GPP_F23_IRQ 0x6D
233 
234 /* Group C */
235 #define GPP_C0_iIRQ 0x6E
236 #define GPP_C1_IRQ 0x6F
237 #define GPP_C2_IRQ 0x70
238 #define GPP_C3_IRQ 0x71
239 #define GPP_C4_IRQ 0x72
240 #define GPP_C5_IRQ 0x73
241 #define GPP_C6_IRQ 0x74
242 #define GPP_C7_IRQ 0x75
243 #define GPP_C8_IRQ 0x76
244 #define GPP_C9_IRQ 0x77
245 #define GPP_C10_IRQ 0x18
246 #define GPP_C11_IRQ 0x19
247 #define GPP_C12_IRQ 0x1A
248 #define GPP_C13_IRQ 0x1B
249 #define GPP_C14_IRQ 0x1C
250 #define GPP_C15_IRQ 0x1D
251 #define GPP_C16_IRQ 0x1E
252 #define GPP_C17_IRQ 0x1F
253 #define GPP_C18_IRQ 0x20
254 #define GPP_C19_IRQ 0x21
255 #define GPP_C20_IRQ 0x22
256 #define GPP_C21_IRQ 0x23
257 #define GPP_C22_IRQ 0x24
258 #define GPP_C23_IRQ 0x25
259 
260 /* Group E */
261 #define GPP_E0_IRQ 0x26
262 #define GPP_E1_IRQ 0x27
263 #define GPP_E2_IRQ 0x28
264 #define GPP_E3_IRQ 0x29
265 #define GPP_E4_IRQ 0x30
266 #define GPP_E5_IRQ 0x31
267 #define GPP_E6_IRQ 0x32
268 #define GPP_E7_IRQ 0x33
269 #define GPP_E8_IRQ 0x34
270 #define GPP_E9_IRQ 0x35
271 #define GPP_E10_IRQ 0x36
272 #define GPP_E11_IRQ 0x37
273 #define GPP_E12_IRQ 0x38
274 #define GPP_E13_IRQ 0x39
275 #define GPP_E14_IRQ 0x3A
276 #define GPP_E15_IRQ 0x3B
277 #define GPP_E16_IRQ 0x3C
278 #define GPP_E17_IRQ 0x3D
279 #define GPP_E18_IRQ 0x3E
280 #define GPP_E19_IRQ 0x3F
281 #define GPP_E20_IRQ 0x40
282 #define GPP_E21_IRQ 0x41
283 #define GPP_E22_IRQ 0x42
284 #define GPP_E23_IRQ 0x43
285 
286 /* Register defines. */
287 #define GPIO_MISCCFG 0x10
288 #define GPE_DW_SHIFT 8
289 #define GPE_DW_MASK 0xfff00
290 #define HOSTSW_OWN_REG_0 0xb0
291 #define GPI_INT_STS_0 0x100
292 #define GPI_INT_EN_0 0x120
293 #define GPI_SMI_STS_0 0x180
294 #define GPI_SMI_EN_0 0x1A0
295 #define GPI_NMI_STS_0 0x1c0
296 #define GPI_NMI_EN_0 0x1e0
297 #define PAD_CFG_BASE 0x700
298 
299 #endif