coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
usb.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _SOC_USB_H_
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#define _SOC_USB_H_
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#include <
stdint.h
>
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/* Per Port HS Transmitter Emphasis */
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#define USB2_EMP_OFF 0
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#define USB2_DE_EMP_ON 1
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#define USB2_PRE_EMP_ON 2
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#define USB2_DE_EMP_ON_PRE_EMP_ON 3
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/* Per Port Half Bit Pre-emphasis */
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#define USB2_FULL_BIT_PRE_EMP 0
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#define USB2_HALF_BIT_PRE_EMP 1
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/* Per Port HS Preemphasis Bias */
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#define USB2_BIAS_0MV 0
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#define USB2_BIAS_11P25MV 1
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#define USB2_BIAS_16P9MV 2
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#define USB2_BIAS_28P15MV 3
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#define USB2_BIAS_39P35MV 5
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#define USB2_BIAS_45MV 6
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#define USB2_BIAS_56P3MV 7
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struct
usb2_port_config
{
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uint8_t
enable
;
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uint8_t
ocpin
;
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uint8_t
tx_bias
;
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uint8_t
tx_emp_enable
;
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uint8_t
pre_emp_bias
;
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uint8_t
pre_emp_bit
;
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};
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/* USB Overcurrent pins definition */
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enum
{
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OC0
= 0,
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OC1
,
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OC2
,
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OC3
,
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OC4
,
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OC5
,
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OC6
,
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OC7
,
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OCMAX
,
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OC_SKIP
= 0xff,
/* Skip OC programming */
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};
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/* Standard USB Port based on length:
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* - External
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* - Back Panel
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* - OTG
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* - M.2
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* - Internal device down */
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#define USB2_PORT_EMPTY { \
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.enable = 0, \
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.ocpin = OC_SKIP, \
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.tx_bias = USB2_BIAS_0MV, \
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.tx_emp_enable = USB2_EMP_OFF, \
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.pre_emp_bias = USB2_BIAS_0MV, \
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
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}
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/* Length = 11.5"-12" */
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#define USB2_PORT_LONG(pin) { \
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.enable = 1, \
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.ocpin = (pin), \
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.tx_bias = USB2_BIAS_39P35MV, \
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.tx_emp_enable = USB2_PRE_EMP_ON, \
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.pre_emp_bias = USB2_BIAS_56P3MV, \
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
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}
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/* Length = 6"-11.49" */
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#define USB2_PORT_MID(pin) { \
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.enable = 1, \
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.ocpin = (pin), \
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.tx_bias = USB2_BIAS_0MV, \
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.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \
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.pre_emp_bias = USB2_BIAS_45MV, \
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.pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \
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}
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/* Length = 3"-5.99" */
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#define USB2_PORT_SHORT(pin) { \
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.enable = 1, \
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.ocpin = (pin), \
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.tx_bias = USB2_BIAS_39P35MV, \
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.tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \
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.pre_emp_bias = USB2_BIAS_39P35MV, \
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.pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \
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}
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/* Max TX and Pre-emp settings */
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#define USB2_PORT_MAX(pin) { \
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.enable = 1, \
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.ocpin = (pin), \
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.tx_bias = USB2_BIAS_56P3MV, \
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.tx_emp_enable = USB2_PRE_EMP_ON, \
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.pre_emp_bias = USB2_BIAS_56P3MV, \
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
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}
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/* Type-C Port, no BC1.2 charge detect module / MUX
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* Length = 3.0" - 9.00" */
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#define USB2_PORT_TYPE_C(pin) { \
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.enable = 1, \
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.ocpin = (pin), \
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.tx_bias = USB2_BIAS_0MV, \
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.tx_emp_enable = USB2_PRE_EMP_ON, \
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.pre_emp_bias = USB2_BIAS_56P3MV, \
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
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}
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struct
usb3_port_config
{
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uint8_t
enable
;
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uint8_t
ocpin
;
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uint8_t
tx_de_emp
;
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uint8_t
tx_downscale_amp
;
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};
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#define USB3_PORT_EMPTY { \
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.enable = 0, \
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.ocpin = OC_SKIP, \
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.tx_de_emp = 0x00, \
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.tx_downscale_amp = 0x00, \
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}
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#define USB3_PORT_DEFAULT(pin) { \
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.enable = 1, \
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.ocpin = (pin), \
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.tx_de_emp = 0x0, \
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.tx_downscale_amp = 0x00, \
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}
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#endif
OC2
@ OC2
Definition:
usb.h:41
OC7
@ OC7
Definition:
usb.h:46
OC3
@ OC3
Definition:
usb.h:42
OC5
@ OC5
Definition:
usb.h:44
OCMAX
@ OCMAX
Definition:
usb.h:47
OC0
@ OC0
Definition:
usb.h:39
OC_SKIP
@ OC_SKIP
Definition:
usb.h:48
OC1
@ OC1
Definition:
usb.h:40
OC6
@ OC6
Definition:
usb.h:45
OC4
@ OC4
Definition:
usb.h:43
stdint.h
uint8_t
unsigned char uint8_t
Definition:
stdint.h:8
usb2_port_config
Definition:
usb.h:27
usb2_port_config::tx_bias
uint8_t tx_bias
Definition:
usb.h:30
usb2_port_config::ocpin
uint8_t ocpin
Definition:
usb.h:29
usb2_port_config::pre_emp_bias
uint8_t pre_emp_bias
Definition:
usb.h:32
usb2_port_config::enable
uint8_t enable
Definition:
usb.h:28
usb2_port_config::pre_emp_bit
uint8_t pre_emp_bit
Definition:
usb.h:33
usb2_port_config::tx_emp_enable
uint8_t tx_emp_enable
Definition:
usb.h:31
usb3_port_config
Definition:
usb.h:130
usb3_port_config::ocpin
uint8_t ocpin
Definition:
usb.h:132
usb3_port_config::tx_downscale_amp
uint8_t tx_downscale_amp
Definition:
usb.h:134
usb3_port_config::tx_de_emp
uint8_t tx_de_emp
Definition:
usb.h:133
usb3_port_config::enable
uint8_t enable
Definition:
usb.h:131
src
soc
intel
elkhartlake
include
soc
usb.h
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