coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
romstage_fsp_params.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <console/console.h>
4 #include <fsp/api.h>
5 #include <soc/romstage.h>
6 #include <spd_bin.h>
7 #include "board_id.h"
8 #include "spd/spd.h"
9 
10 void mainboard_memory_init_params(FSPM_UPD *mupd)
11 {
12  FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
13  u8 spd_index = (get_board_id() & 0x1F) & 0x7;
14  printk(BIOS_DEBUG, "spd index is 0x%x\n", spd_index);
15 
16  if (spd_index > 0 && spd_index != 2) {
17  mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE;
18 
19  /* Memory leak is ok since we have memory mapped boot media */
20  mem_cfg->MemorySpdPtr00 = spd_cbfs_map(spd_index);
21  if (!mem_cfg->MemorySpdPtr00)
22  die("spd.bin not found\n");
23  mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
24 
25  mem_cfg->SpdAddressTable[0] = 0x0;
26  mem_cfg->SpdAddressTable[1] = 0x0;
27  mem_cfg->SpdAddressTable[2] = 0x0;
28  mem_cfg->SpdAddressTable[3] = 0x0;
29  } else {
30  mem_cfg->MemorySpdPtr00 = 0;
31  mem_cfg->MemorySpdPtr01 = 0;
32  mem_cfg->MemorySpdPtr10 = 0;
33  mem_cfg->MemorySpdPtr11 = 0;
34 
35  mem_cfg->SpdAddressTable[0] = 0xA0;
36  mem_cfg->SpdAddressTable[1] = 0xA2;
37  mem_cfg->SpdAddressTable[2] = 0xA4;
38  mem_cfg->SpdAddressTable[3] = 0xA6;
39  }
40  mem_cfg->DqPinsInterleaved = 0;
41  mem_cfg->CaVrefConfig = 0x2; /* VREF_CA->CHA/CHB */
42  mem_cfg->ECT = 1; /* Early Command Training Enabled */
43  mem_cfg->RefClk = 0; /* Auto Select CLK freq */
44 
45  mainboard_fill_dq_map_ch0(&mem_cfg->DqByteMapCh0);
46  mainboard_fill_dq_map_ch1(&mem_cfg->DqByteMapCh1);
47  mainboard_fill_dqs_map_ch0(&mem_cfg->DqsMapCpu2DramCh0);
48  mainboard_fill_dqs_map_ch1(&mem_cfg->DqsMapCpu2DramCh1);
49  mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
50  mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
51 }
#define printk(level,...)
Definition: stdlib.h:16
void __noreturn die(const char *fmt,...)
Definition: die.c:17
#define FSP_M_CONFIG
Definition: fsp_upd.h:8
void mainboard_memory_init_params(FSPM_UPD *memupd)
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
Definition: loglevel.h:128
static void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
Definition: romstage.c:8
static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
Definition: romstage.c:15
static const int spd_index[32]
Definition: memory.c:10
static uint8_t get_board_id(void)
Definition: boardid.c:14
void mainboard_fill_dq_map_ch1(u8 *dq_map_ptr)
void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr)
void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr)
void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr)
uintptr_t spd_cbfs_map(u8 spd_index)
Definition: spd_bin.c:217
uint8_t u8
Definition: stdint.h:45