coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
ramstage.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
delay.h
>
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#include <gpio.h>
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#include <baseboard/variants.h>
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#include <soc/gpio.h>
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void
variant_ramstage_init
(
void
)
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{
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/*
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* Assert FPMCU reset and enable power to FPMCU,
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* wait for power rail to stabilize,
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* and then deassert FPMCU reset.
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* Waiting for the power rail to stabilize can take a while.
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*/
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gpio_output
(
GPP_C23
, 0);
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gpio_output
(
GPP_A21
, 1);
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mdelay
(1);
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gpio_output
(
GPP_C23
, 1);
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}
GPP_C23
#define GPP_C23
Definition:
gpio_soc_defs.h:560
GPP_A21
#define GPP_A21
Definition:
gpio_soc_defs.h:140
delay.h
mdelay
void mdelay(unsigned int msecs)
Definition:
delay.c:2
gpio_output
void gpio_output(gpio_t gpio, int value)
Definition:
gpio.c:194
variant_ramstage_init
void __weak variant_ramstage_init(void)
Definition:
ramstage.c:19
src
mainboard
google
volteer
variants
voema
ramstage.c
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