coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
clock.h
Go to the documentation of this file.
1 /* Source : APQ8064 LK Boot */
2 /* SPDX-License-Identifier: BSD-3-Clause */
3 
4 #ifndef __IPQ40XX_CLOCK_H_
5 #define __IPQ40XX_CLOCK_H_
6 
7 #include <soc/iomap.h>
8 #include <types.h>
9 
10 /* UART clock @ 7.3728 MHz */
11 #define UART_DM_CLK_RX_TX_BIT_RATE 0xFF
12 
13 /* UART specific definitions */
14 
15 #define Uart_ns_val NS(BIT_POS_31, BIT_POS_16, N_VALUE, M_VALUE, \
16  5, 4, 3, 1, 2, 0, 3)
17 #define Uart_clk_ns_mask (BM(BIT_POS_31, BIT_POS_16) | \
18  BM(BIT_POS_6, BIT_POS_0))
19 #define Uart_mnd_en_mask (BIT(8) * !!(625))
20 #define Uart_en_mask BIT(11)
21 #define MD16(m, n) (BVAL(BIT_POS_31, BIT_POS_16, m) | \
22  BVAL(BIT_POS_15, BIT_POS_0, ~(n)))
23 #define Uart_ns_val_rumi NS(BIT_POS_31, BIT_POS_16, N_VALUE, M_VALUE, \
24  5, 4, 3, 1, 2, 0, 0)
25 #define GSBIn_UART_APPS_MD_REG(n) REG(0x29D0+(0x20*((n)-1)))
26 #define GSBIn_UART_APPS_NS_REG(n) REG(0x29D4+(0x20*((n)-1)))
27 #define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1)))
28 #define BB_PLL_ENA_SC0_REG REG(0x34C0)
29 #define BB_PLL8_STATUS_REG REG(0x3158)
30 #define REG(off) ((void *)(MSM_CLK_CTL_BASE + (off)))
31 #define PLL8_STATUS_BIT 16
32 
33 #define PLL_LOCK_DET_STATUS_REG REG(0x03420)
34 #define SFAB_AHB_S3_FCLK_CTL_REG REG(0x0216C)
35 #define CFPB_CLK_NS_REG REG(0x0264C)
36 #define CFPB0_HCLK_CTL_REG REG(0x02650)
37 #define SFAB_CFPB_S_HCLK_CTL_REG REG(0x026C0)
38 #define CFPB_SPLITTER_HCLK_CTL_REG REG(0x026E0)
39 #define EBI2_CLK_CTL_REG REG(0x03B00)
40 
41 #define USB30_MASTER_CLK_CTL_REG REG(0x3b24)
42 #define USB30_MASTER_CLK_MD REG(0x3b28)
43 #define USB30_MASTER_CLK_NS REG(0x3b2c)
44 #define USB30_1_MASTER_CLK_CTL_REG REG(0x3b34)
45 #define USB30_MOC_UTMI_CLK_MD REG(0x3b40)
46 #define USB30_MOC_UTMI_CLK_NS REG(0x3b44)
47 #define USB30_MOC_UTMI_CLK_CTL REG(0x3b48)
48 #define USB30_1_MOC_UTMI_CLK_CTL REG(0x3b4c)
49 #define USB30_RESET REG(0x3b50)
50 
51 #define ALWAYS_ON_CLK_BRANCH_ENA(i) ((i) << 8)
52 
53 #define CLK_BRANCH_ENA_MASK 0x00000010
54 #define CLK_BRANCH_ENA_ENABLE 0x00000010
55 #define CLK_BRANCH_ENA_DISABLE 0x00000000
56 #define CLK_BRANCH_ENA(i) ((i) << 4)
57 
58 /* Register: CFPB_CLK_NS */
59 #define CLK_DIV_MASK 0x00000003
60 #define CLK_DIV_DIV_1 0x00000000
61 #define CLK_DIV_DIV_2 0x00000001
62 #define CLK_DIV_DIV_3 0x00000002
63 #define CLK_DIV_DIV_4 0x00000003
64 #define CLK_DIV(i) ((i) << 0)
65 
66 #define MN_MODE_DUAL_EDGE 0x2
67 #define BIT_POS_31 31
68 #define BIT_POS_16 16
69 #define BIT_POS_6 6
70 #define BIT_POS_0 0
71 #define BIT_POS_15 15
72 
73 #define BM(m, l) (((((unsigned int)-1) << (31-m)) >> (31-m+l)) << l)
74 #define BVAL(m, l, val) (((val) << l) & BM(m, l))
75 
76 /* MD Registers */
77 #define MD4(m_lsb, m, n_lsb, n) \
78  (BVAL((m_lsb+3), m_lsb, m) | BVAL((n_lsb+3), n_lsb, ~(n)))
79 
80 #define MD8(m_lsb, m, n_lsb, n) \
81  (BVAL((m_lsb+7), m_lsb, m) | BVAL((n_lsb+7), n_lsb, ~(n)))
82 
83 /* NS Registers */
84 #define NS(n_msb, n_lsb, n, m, mde_lsb, d_msb, d_lsb, d, s_msb, s_lsb, s) \
85  (BVAL(n_msb, n_lsb, ~(n-m)) \
86  | (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n)) \
87  | BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
88 
89 #define NS_MM(n_msb, n_lsb, n, m, d_msb, d_lsb, d, s_msb, s_lsb, s) \
90  (BVAL(n_msb, n_lsb, ~(n-m)) | BVAL(d_msb, d_lsb, (d-1)) \
91  | BVAL(s_msb, s_lsb, s))
92 
93 #define NS_DIVSRC(d_msb , d_lsb, d, s_msb, s_lsb, s) \
94  (BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
95 
96 #define NS_DIV(d_msb , d_lsb, d) \
97  BVAL(d_msb, d_lsb, (d-1))
98 
99 #define NS_SRC_SEL(s_msb, s_lsb, s) \
100  BVAL(s_msb, s_lsb, s)
101 
102 #define GMAC_AHB_RESET 0x903E24
103 
104 #define SRC_SEL_PLL0 (0x2 << 0)
105 #define MNCNTR_MODE_DUAL_EDGE (0x2 << 5)
106 #define MNCNTR_ENABLE (0x1 << 8)
107 #define MNCNTR_RST_ACTIVE (0x1 << 7)
108 #define N_VAL 15
109 
110 #define GMAC_CORE_RESET(n) \
111  ((void *)(0x903CBC + ((n) * 0x20)))
112 
113 #define GMACSEC_CORE_RESET(n) \
114  ((void *)(0x903E28 + ((n - 1) * 4)))
115 
116 #define GMAC_COREn_CLCK_SRC_CTL(N) \
117  (0x00900000 + (0x3CA0 + (32*(N-1))))
118 
119 #define GMAC_COREn_CLCK_SRC0_MD(N) \
120  (0x00900000 + (0x3CA4 + (32*(N-1))))
121 
122 #define GMAC_COREn_CLCK_SRC1_MD(N) \
123  (0x00900000 + (0x3CA8 + (32*(N-1))))
124 
125 #define GMAC_COREn_CLCK_SRC0_NS(N) \
126  (0x00900000 + (0x3CAC + (32*(N-1))))
127 
128 #define GMAC_COREn_CLCK_SRC1_NS(N) \
129  (0x00900000 + (0x3CB0 + (32*(N-1))))
130 
131 #define DISABLE_DUAL_MN8_SEL (0)
132 #define DISABLE_CLK_LOW_PWR (0 << 2)
133 #define GMAC_CORE_CLCK_ROOT_ENABLE (1 << 1)
134 
135 /* GMAC_COREn_CLK_SRC[0,1]_MD register bits (Assuming 133MHz) */
136 #define GMAC_CORE_CLCK_M 0x32
137 #define GMAC_CORE_CLCK_D 0 /* NOT(2*D) value */
138 #define GMAC_CORE_CLCK_M_SHIFT 16
139 #define GMAC_CORE_CLCK_D_SHIFT 0
140 #define GMAC_CORE_CLCK_M_VAL \
141  (GMAC_CORE_CLCK_M << GMAC_CORE_CLCK_M_SHIFT)
142 #define GMAC_CORE_CLCK_D_VAL \
143  (GMAC_CORE_CLCK_D << GMAC_CORE_CLCK_D_SHIFT)
144 
145 /* GMAC_COREn_CLK_SRC[0,1]_NS register bits (Assuming 133MHz) */
146 #define GMAC_CORE_CLCK_N 0x4 /* NOT(N-M) value, N=301 */
147 #define GMAC_CORE_CLCK_N_SHIFT 16
148 #define GMAC_CORE_CLCK_N_VAL \
149  (GMAC_CORE_CLCK_N << GMAC_CORE_CLCK_N_SHIFT)
150 /* Enable M/N counter */
151 #define GMAC_CORE_CLCK_MNCNTR_EN 0x00000100
152 /* Activate reset for M/N counter */
153 #define GMAC_CORE_CLCK_MNCNTR_RST 0x00000080
154 /* M/N counter mode mask */
155 #define GMAC_CORE_CLCK_MNCNTR_MODE_MASK 0x00000060
156 #define GMAC_CORE_CLCK_MNCNTR_MODE_SHIFT 5
157 /* M/N counter mode dual-edge */
158 #define GMAC_CORE_CLCK_MNCNTR_MODE_DUAL \
159  (2 << GMAC_CORE_CLCK_MNCNTR_MODE_SHIFT)
160 /* Pre divider select mask */
161 #define GMAC_CORE_CLCK_PRE_DIV_SEL_MASK 0x00000018
162 #define GMAC_CORE_CLCK_PRE_DIV_SEL_SHIFT 3
163 /* Pre divider bypass */
164 #define GMAC_CORE_CLCK_PRE_DIV_SEL_BYP \
165  (0 << GMAC_CORE_CLCK_PRE_DIV_SEL_SHIFT)
166 /* clk source Mux select mask */
167 #define GMAC_CORE_CLCK_SRC_SEL_MASK 0x00000007
168 #define GMAC_CORE_CLCK_SRC_SEL_SHIFT 0
169 /* output of clk source Mux is PLL0 */
170 #define GMAC_CORE_CLCK_SRC_SEL_PLL0 \
171  (2 << GMAC_CORE_CLCK_SRC_SEL_SHIFT)
172 #define GMAC_COREn_CLCK_CTL(N) \
173  (0x00900000 + (0x3CB4 + (32*(N-1))))
174 
175 #define GMAC_COREn_CLCK_INV_DISABLE (0 << 5)
176 #define GMAC_COREn_CLCK_BRANCH_ENA (1 << 4)
177 
178 /* Uart specific clock settings */
179 
180 void uart_pll_vote_clk_enable(unsigned int);
181 void uart_clock_config(unsigned int blsp_uart, unsigned int m, unsigned int n,
182  unsigned int d);
183 void nand_clock_config(void);
184 void usb_clock_config(void);
185 int audio_clock_config(unsigned int frequency);
186 int blsp_i2c_clock_config(blsp_qup_id_t id);
187 
188 #endif /* __PLATFORM_IPQ40XX_CLOCK_H_ */
blsp_qup_id_t
blsp_qup_id_t
Definition: blsp.h:6
blsp_i2c_clock_config
int blsp_i2c_clock_config(blsp_qup_id_t id)
Definition: clock.c:91
nand_clock_config
void nand_clock_config(void)
nand_clock_config - configure NAND controller clocks
Definition: clock.c:56
audio_clock_config
int audio_clock_config(unsigned int frequency)
Definition: lcc.c:260
uart_clock_config
void uart_clock_config(unsigned int blsp_uart, unsigned int m, unsigned int n, unsigned int d)
uart_clock_config - configures UART clocks
Definition: clock.c:17
uart_pll_vote_clk_enable
void uart_pll_vote_clk_enable(unsigned int)
uart_pll_vote_clk_enable - enables PLL8
Definition: clock.c:11
usb_clock_config
void usb_clock_config(void)
usb_clock_config - configure USB controller clocks and reset the controller
Definition: clock.c:68
m
#define m(clkreg, src_bits, pmcreg, dst_bits)