coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
pci_devs.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _BAYTRAIL_PCI_DEVS_H_
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#define _BAYTRAIL_PCI_DEVS_H_
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/* All these devices live on bus 0 with the associated device and function */
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/* SoC transaction router */
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#define SOC_DEV 0x0
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#define SOC_FUNC 0
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/* Graphics and Display */
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#define GFX_DEV 0x2
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#define GFX_FUNC 0
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/* MMC Port */
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#define MMC_DEV 0x10
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#define MMC_FUNC 0
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/* SDIO Port */
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#define SDIO_DEV 0x11
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#define SDIO_FUNC 0
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/* SD Port */
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#define SD_DEV 0x12
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#define SD_FUNC 0
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/* SATA */
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#define SATA_DEV 0x13
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#define SATA_FUNC 0
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/* xHCI */
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#define XHCI_DEV 0x14
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#define XHCI_FUNC 0
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/* LPE Audio */
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#define LPE_DEV 0x15
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#define LPE_FUNC 0
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/* MMC45 Port */
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#define MMC45_DEV 0x17
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#define MMC45_FUNC 0
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/* Serial IO 1 */
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#define SIO1_DEV 0x18
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# define SIO_DMA1_DEV SIO1_DEV
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# define SIO_DMA1_FUNC 0
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# define I2C1_DEV SIO1_DEV
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# define I2C1_FUNC 1
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# define I2C2_DEV SIO1_DEV
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# define I2C2_FUNC 2
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# define I2C3_DEV SIO1_DEV
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# define I2C3_FUNC 3
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# define I2C4_DEV SIO1_DEV
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# define I2C4_FUNC 4
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# define I2C5_DEV SIO1_DEV
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# define I2C5_FUNC 5
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# define I2C6_DEV SIO1_DEV
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# define I2C6_FUNC 6
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# define I2C7_DEV SIO1_DEV
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# define I2C7_FUNC 7
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/* Trusted Execution Engine */
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#define TXE_DEV 0x1a
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#define TXE_FUNC 0
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/* HD Audio */
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#define HDA_DEV 0x1b
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#define HDA_FUNC 0
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/* PCIe Ports */
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#define PCIE_DEV 0x1c
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# define PCIE_PORT1_DEV PCIE_DEV
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# define PCIE_PORT1_FUNC 0
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# define PCIE_PORT2_DEV PCIE_DEV
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# define PCIE_PORT2_FUNC 1
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# define PCIE_PORT3_DEV PCIE_DEV
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# define PCIE_PORT3_FUNC 2
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# define PCIE_PORT4_DEV PCIE_DEV
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# define PCIE_PORT4_FUNC 3
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/* EHCI */
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#define EHCI_DEV 0x1d
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#define EHCI_FUNC 0
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/* Serial IO 2 */
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#define SIO2_DEV 0x1e
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# define SIO_DMA2_DEV SIO2_DEV
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# define SIO_DMA2_FUNC 0
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# define PWM1_DEV SIO2_DEV
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# define PWM1_FUNC 1
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# define PWM2_DEV SIO2_DEV
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# define PWM2_FUNC 2
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# define HSUART1_DEV SIO2_DEV
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# define HSUART1_FUNC 3
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# define HSUART2_DEV SIO2_DEV
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# define HSUART2_FUNC 4
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# define SPI_DEV SIO2_DEV
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# define SPI_FUNC 5
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/* Platform Controller Unit */
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#define PCU_DEV 0x1f
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# define LPC_DEV PCU_DEV
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# define LPC_FUNC 0
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# define SMBUS_DEV PCU_DEV
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# define SMBUS_FUNC 3
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#define SOC_DEVID 0x0f00
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#define GFX_DEVID 0x0f31
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#define MMC_DEVID 0x0f14
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#define SDIO_DEVID 0x0f15
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#define SD_DEVID 0x0f16
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#define IDE1_DEVID 0x0f20
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#define IDE2_DEVID 0x0f21
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#define AHCI1_DEVID 0x0f22
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#define AHCI2_DEVID 0x0f23
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#define XHCI_DEVID 0x0f35
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#define LPE_DEVID 0x0f28
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#define MMC45_DEVID 0x0f50
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#define SIO_DMA1_DEVID 0x0f40
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#define I2C1_DEVID 0x0f41
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#define I2C2_DEVID 0x0f42
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#define I2C3_DEVID 0x0f43
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#define I2C4_DEVID 0x0f44
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#define I2C5_DEVID 0x0f45
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#define I2C6_DEVID 0x0f46
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#define I2C7_DEVID 0x0f47
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#define TXE_DEVID 0x0f18
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#define HDA_DEVID 0x0f04
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#define PCIE_PORT1_DEVID 0x0f48
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#define PCIE_PORT2_DEVID 0x0f4a
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#define PCIE_PORT3_DEVID 0x0f4c
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#define PCIE_PORT4_DEVID 0x0f4e
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#define EHCI_DEVID 0x0f34
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#define SIO_DMA2_DEVID 0x0f06
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#define PWM1_DEVID 0x0f08
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#define PWM2_DEVID 0x0f09
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#define HSUART1_DEVID 0x0f0a
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#define HSUART2_DEVID 0x0f0c
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#define SPI_DEVID 0xf0e
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#define LPC_DEVID 0x0f1c
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#define SMBUS_DEVID 0x0f12
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#endif
/* _BAYTRAIL_PCI_DEVS_H_ */
src
soc
intel
baytrail
include
soc
pci_devs.h
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