coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
acpimmio_map.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #ifndef AMD_BLOCK_ACPIMMIO_MAP_H
4 #define AMD_BLOCK_ACPIMMIO_MAP_H
5 
6 /*
7  * The following AcpiMmio register block mapping represents definitions
8  * that have been documented in AMD publications. All blocks aren't
9  * implemented in all products, so the caller should be careful not to
10  * inadvertently access a non-existent block. The definitions within
11  * each block are also subject to change across products. Please refer
12  * to the appropriate RRG, the BKDG, or PPR for the product.
13  *
14  * The base address is configurable in older products, but defaults to
15  * 0xfed80000. The address is fixed at 0xfed80000 in newer products.
16  *
17  * +---------------------------------------------------------------------------+
18  * |0x000 SMBus PCI space |
19  * | * Dual-mapped to PCI configuration header of D14F0 |
20  * +---------------------------------------------------------------------------+
21  * |0x100 GPIO configuration registers |
22  * | * old style, never implemented with newer style |
23  * | * discrete controller hubs and Family 16h Models 00h-0Fh. |
24  * +---------------------------------------------------------------------------+
25  * |0x200 SMI configuration registers |
26  * +---------------------------------------------------------------------------+
27  * |0x300 Power Management registers |
28  * | * Dual-mapped via IO Index/Data 0xcd6/0xcd7 (byte access only) |
29  * +---------------------------------------------------------------------------+
30  * |0x400 Power Management 2 registers |
31  * +---------------------------------------------------------------------------+
32  * |0x500 BIOS RAM |
33  * | * General-purpose storage in S3 domain |
34  * | * Byte access only |
35  * +---------------------------------------------------------------------------+
36  * |0x600 CMOS RAM |
37  * | * Dual-mapped to storage at Alt RTC Index/Data (0x72/0x73) |
38  * | * Byte access only |
39  * +---------------------------------------------------------------------------+
40  * |0x700 CMOS |
41  * | * Dual-mapped to storage at RTC Index/Data (0x70/0x71) |
42  * | * Byte access only |
43  * +---------------------------------------------------------------------------+
44  * |0x800 Standard ACPI registers |
45  * | * Dual-mapped to I/O ACPI registers |
46  * +---------------------------------------------------------------------------+
47  * |0x900 ASF controller registers |
48  * | * Dual-mapped to I/O ASF controller registers |
49  * +---------------------------------------------------------------------------+
50  * |0xa00 SMBus controller registers |
51  * | * Dual-mapped to I/O SMBus controller registers |
52  * +---------------------------------------------------------------------------+
53  * |0xb00 WDT registers |
54  * | * Dual-mapped to WDT registers, typ. enabled at 0xfeb00000 |
55  * +---------------------------------------------------------------------------+
56  * |0xc00 HPET registers |
57  * | * Dual-mapped to HPET registers, typ. enabled at 0xfed00000 |
58  * +---------------------------------------------------------------------------+
59  * |0xd00 MUX configuration registers for GPIO signals |
60  * +---------------------------------------------------------------------------+
61  * |0xe00 Miscellaneous registers |
62  * +---------------------------------------------------------------------------+
63  * |0x1000 Serial debug bus |
64  * +---------------------------------------------------------------------------+
65  * |0x1200 remote GPIO configuration registers |
66  * | * contains both GPIO and MUX registers |
67  * +---------------------------------------------------------------------------+
68  * |0x1400 DP-VGA |
69  * +---------------------------------------------------------------------------+
70  * |0x1500 GPIO configuration registers bank 0 |
71  * | * new style, never implemented with older style |
72  * | * SoCs starting with Family 16h Models 30h-3Fh |
73  * +---------------------------------------------------------------------------+
74  * |0x1600 GPIO configuration registers bank 1 (following bank 0) |
75  * +---------------------------------------------------------------------------+
76  * |0x1700 GPIO configuration registers bank 2 (following bank 1) |
77  * +---------------------------------------------------------------------------+
78  * |0x1800 GPIO configuration registers bank 3 (following bank 2) |
79  * +---------------------------------------------------------------------------+
80  * |0x1c00 xHCI Power Management registers |
81  * +---------------------------------------------------------------------------+
82  * |0x1d00 Wake device (AC DC timer) |
83  * +---------------------------------------------------------------------------+
84  * |0x1e00 Always On Always Connected (AOAC) registers |
85  * +---------------------------------------------------------------------------+
86  */
87 
88 /*
89  * MMIO register blocks are at fixed offsets from 0xfed80000 and are enabled
90  * in PMx24[0] (older implementations) and PMx04[1] (newer implementations).
91  * PM registers are also accessible via IO CD6/CD7.
92  *
93  * All products do not support all blocks below, however AMD has avoided
94  * redefining addresses and consumes new ranges as necessary.
95  *
96  * Definitions within each block are not guaranteed to remain consistent
97  * across family/model products.
98  */
99 
100 #define AMD_SB_ACPI_MMIO_ADDR 0xfed80000
101 
102 #ifdef __ACPI__
103 /* ASL MemoryFixed32() fails if these are additions. */
104 #define ACPIMMIO_MISC_BASE 0xfed80e00
105 #define ACPIMMIO_GPIO0_BASE 0xfed81500
106 #endif
107 
108 #define ACPIMMIO_SM_PCI_BANK 0x0000
109 #define ACPIMMIO_GPIO_100_BANK 0x0100
110 #define ACPIMMIO_SMI_BANK 0x0200
111 #define ACPIMMIO_PMIO_BANK 0x0300
112 #define ACPIMMIO_PMIO2_BANK 0x0400
113 #define ACPIMMIO_BIOSRAM_BANK 0x0500
114 #define ACPIMMIO_CMOSRAM_BANK 0x0600
115 #define ACPIMMIO_CMOS_BANK 0x0700
116 #define ACPIMMIO_ACPI_BANK 0x0800
117 #define ACPIMMIO_ASF_BANK 0x0900
118 #define ACPIMMIO_SMBUS_BANK 0x0a00
119 #define ACPIMMIO_WDT_BANK 0x0b00
120 #define ACPIMMIO_HPET_BANK 0x0c00
121 #define ACPIMMIO_IOMUX_BANK 0x0d00
122 #define ACPIMMIO_MISC_BANK 0x0e00
123 #define ACPIMMIO_REMOTE_GPIO_BANK 0x1200
124 #define ACPIMMIO_DPVGA_BANK 0x1400
125 #define ACPIMMIO_GPIO0_BANK 0x1500
126 #define ACPIMMIO_XHCIPM_BANK 0x1c00
127 #define ACPIMMIO_ACDCTMR_BANK 0x1d00
128 #define ACPIMMIO_AOAC_BANK 0x1e00
129 
130 #define ACPIMMIO_BASE(bank) (AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ ## bank ## _BANK)
131 
132 #endif /* AMD_BLOCK_ACPIMMIO_MAP_H */