coreboot
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acpimmio_map.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef AMD_BLOCK_ACPIMMIO_MAP_H
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#define AMD_BLOCK_ACPIMMIO_MAP_H
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/*
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* The following AcpiMmio register block mapping represents definitions
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* that have been documented in AMD publications. All blocks aren't
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* implemented in all products, so the caller should be careful not to
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* inadvertently access a non-existent block. The definitions within
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* each block are also subject to change across products. Please refer
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* to the appropriate RRG, the BKDG, or PPR for the product.
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*
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* The base address is configurable in older products, but defaults to
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* 0xfed80000. The address is fixed at 0xfed80000 in newer products.
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*
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* +---------------------------------------------------------------------------+
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* |0x000 SMBus PCI space |
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* | * Dual-mapped to PCI configuration header of D14F0 |
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* +---------------------------------------------------------------------------+
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* |0x100 GPIO configuration registers |
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* | * old style, never implemented with newer style |
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* | * discrete controller hubs and Family 16h Models 00h-0Fh. |
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* +---------------------------------------------------------------------------+
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* |0x200 SMI configuration registers |
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* +---------------------------------------------------------------------------+
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* |0x300 Power Management registers |
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* | * Dual-mapped via IO Index/Data 0xcd6/0xcd7 (byte access only) |
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* +---------------------------------------------------------------------------+
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* |0x400 Power Management 2 registers |
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* +---------------------------------------------------------------------------+
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* |0x500 BIOS RAM |
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* | * General-purpose storage in S3 domain |
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* | * Byte access only |
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* +---------------------------------------------------------------------------+
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* |0x600 CMOS RAM |
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* | * Dual-mapped to storage at Alt RTC Index/Data (0x72/0x73) |
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* | * Byte access only |
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* +---------------------------------------------------------------------------+
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* |0x700 CMOS |
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* | * Dual-mapped to storage at RTC Index/Data (0x70/0x71) |
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* | * Byte access only |
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* +---------------------------------------------------------------------------+
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* |0x800 Standard ACPI registers |
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* | * Dual-mapped to I/O ACPI registers |
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* +---------------------------------------------------------------------------+
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* |0x900 ASF controller registers |
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* | * Dual-mapped to I/O ASF controller registers |
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* +---------------------------------------------------------------------------+
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* |0xa00 SMBus controller registers |
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* | * Dual-mapped to I/O SMBus controller registers |
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* +---------------------------------------------------------------------------+
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* |0xb00 WDT registers |
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* | * Dual-mapped to WDT registers, typ. enabled at 0xfeb00000 |
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* +---------------------------------------------------------------------------+
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* |0xc00 HPET registers |
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* | * Dual-mapped to HPET registers, typ. enabled at 0xfed00000 |
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* +---------------------------------------------------------------------------+
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* |0xd00 MUX configuration registers for GPIO signals |
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* +---------------------------------------------------------------------------+
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* |0xe00 Miscellaneous registers |
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* +---------------------------------------------------------------------------+
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* |0x1000 Serial debug bus |
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* +---------------------------------------------------------------------------+
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* |0x1200 remote GPIO configuration registers |
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* | * contains both GPIO and MUX registers |
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* +---------------------------------------------------------------------------+
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* |0x1400 DP-VGA |
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* +---------------------------------------------------------------------------+
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* |0x1500 GPIO configuration registers bank 0 |
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* | * new style, never implemented with older style |
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* | * SoCs starting with Family 16h Models 30h-3Fh |
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* +---------------------------------------------------------------------------+
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* |0x1600 GPIO configuration registers bank 1 (following bank 0) |
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* +---------------------------------------------------------------------------+
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* |0x1700 GPIO configuration registers bank 2 (following bank 1) |
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* +---------------------------------------------------------------------------+
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* |0x1800 GPIO configuration registers bank 3 (following bank 2) |
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* +---------------------------------------------------------------------------+
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* |0x1c00 xHCI Power Management registers |
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* +---------------------------------------------------------------------------+
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* |0x1d00 Wake device (AC DC timer) |
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* +---------------------------------------------------------------------------+
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* |0x1e00 Always On Always Connected (AOAC) registers |
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* +---------------------------------------------------------------------------+
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*/
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/*
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* MMIO register blocks are at fixed offsets from 0xfed80000 and are enabled
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* in PMx24[0] (older implementations) and PMx04[1] (newer implementations).
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* PM registers are also accessible via IO CD6/CD7.
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*
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* All products do not support all blocks below, however AMD has avoided
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* redefining addresses and consumes new ranges as necessary.
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*
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* Definitions within each block are not guaranteed to remain consistent
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* across family/model products.
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*/
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#define AMD_SB_ACPI_MMIO_ADDR 0xfed80000
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#ifdef __ACPI__
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/* ASL MemoryFixed32() fails if these are additions. */
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#define ACPIMMIO_MISC_BASE 0xfed80e00
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#define ACPIMMIO_GPIO0_BASE 0xfed81500
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#endif
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#define ACPIMMIO_SM_PCI_BANK 0x0000
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#define ACPIMMIO_GPIO_100_BANK 0x0100
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#define ACPIMMIO_SMI_BANK 0x0200
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#define ACPIMMIO_PMIO_BANK 0x0300
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#define ACPIMMIO_PMIO2_BANK 0x0400
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#define ACPIMMIO_BIOSRAM_BANK 0x0500
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#define ACPIMMIO_CMOSRAM_BANK 0x0600
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#define ACPIMMIO_CMOS_BANK 0x0700
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#define ACPIMMIO_ACPI_BANK 0x0800
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#define ACPIMMIO_ASF_BANK 0x0900
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#define ACPIMMIO_SMBUS_BANK 0x0a00
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#define ACPIMMIO_WDT_BANK 0x0b00
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#define ACPIMMIO_HPET_BANK 0x0c00
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#define ACPIMMIO_IOMUX_BANK 0x0d00
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#define ACPIMMIO_MISC_BANK 0x0e00
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#define ACPIMMIO_REMOTE_GPIO_BANK 0x1200
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#define ACPIMMIO_DPVGA_BANK 0x1400
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#define ACPIMMIO_GPIO0_BANK 0x1500
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#define ACPIMMIO_XHCIPM_BANK 0x1c00
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#define ACPIMMIO_ACDCTMR_BANK 0x1d00
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#define ACPIMMIO_AOAC_BANK 0x1e00
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#define ACPIMMIO_BASE(bank) (AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ ## bank ## _BANK)
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#endif
/* AMD_BLOCK_ACPIMMIO_MAP_H */
src
soc
amd
common
block
include
amdblocks
acpimmio_map.h
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