coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
rcba.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef _BROADWELL_RCBA_H_
4 #define _BROADWELL_RCBA_H_
5 
6 #include <southbridge/intel/common/rcba.h>
7 
8 #define RPC 0x0400 /* 32bit */
9 #define RPFN 0x0404 /* 32bit */
10 
11 /* Root Port configuration space hide */
12 #define RPFN_HIDE(port) (1 << (((port) * 4) + 3))
13 /* Get the function number assigned to a Root Port */
14 #define RPFN_FNGET(reg, port) (((reg) >> ((port) * 4)) & 7)
15 /* Set the function number for a Root Port */
16 #define RPFN_FNSET(port, func) (((func) & 7) << ((port) * 4))
17 /* Root Port function number mask */
18 #define RPFN_FNMASK(port) (7 << ((port) * 4))
19 
20 #define NOINT 0
21 #define INTA 1
22 #define INTB 2
23 #define INTC 3
24 #define INTD 4
25 
26 #define DIR_IDR 12 /* Interrupt D Pin Offset */
27 #define DIR_ICR 8 /* Interrupt C Pin Offset */
28 #define DIR_IBR 4 /* Interrupt B Pin Offset */
29 #define DIR_IAR 0 /* Interrupt A Pin Offset */
30 
31 #define PIRQA 0
32 #define PIRQB 1
33 #define PIRQC 2
34 #define PIRQD 3
35 #define PIRQE 4
36 #define PIRQF 5
37 #define PIRQG 6
38 #define PIRQH 7
39 
40 #define LCAP 0x21a4
41 
42 /* IO Buffer Programming */
43 #define IOBPIRI 0x2330
44 #define IOBPD 0x2334
45 #define IOBPS 0x2338
46 #define IOBPS_READY 0x0001
47 #define IOBPS_TX_MASK 0x0006
48 #define IOBPS_MASK 0xff00
49 #define IOBPS_READ 0x0600
50 #define IOBPS_WRITE 0x0700
51 #define IOBPU 0x233a
52 #define IOBPU_MAGIC 0xf000
53 #define IOBP_PCICFG_READ 0x0400
54 #define IOBP_PCICFG_WRITE 0x0500
55 
56 #define D31IP 0x3100 /* 32bit */
57 #define D31IP_TTIP 24 /* Thermal Throttle Pin */
58 #define D31IP_SIP2 20 /* SATA Pin 2 */
59 #define D31IP_SMIP 12 /* SMBUS Pin */
60 #define D31IP_SIP 8 /* SATA Pin */
61 #define D30IP 0x3104 /* 32bit */
62 #define D30IP_PIP 0 /* PCI Bridge Pin */
63 #define D29IP 0x3108 /* 32bit */
64 #define D29IP_E1P 0 /* EHCI #1 Pin */
65 #define D28IP 0x310c /* 32bit */
66 #define D28IP_P8IP 28 /* PCI Express Port 8 */
67 #define D28IP_P7IP 24 /* PCI Express Port 7 */
68 #define D28IP_P6IP 20 /* PCI Express Port 6 */
69 #define D28IP_P5IP 16 /* PCI Express Port 5 */
70 #define D28IP_P4IP 12 /* PCI Express Port 4 */
71 #define D28IP_P3IP 8 /* PCI Express Port 3 */
72 #define D28IP_P2IP 4 /* PCI Express Port 2 */
73 #define D28IP_P1IP 0 /* PCI Express Port 1 */
74 #define D27IP 0x3110 /* 32bit */
75 #define D27IP_ZIP 0 /* HD Audio Pin */
76 #define D26IP 0x3114 /* 32bit */
77 #define D26IP_E2P 0 /* EHCI #2 Pin */
78 #define D25IP 0x3118 /* 32bit */
79 #define D25IP_LIP 0 /* GbE LAN Pin */
80 #define D22IP 0x3124 /* 32bit */
81 #define D22IP_KTIP 12 /* KT Pin */
82 #define D22IP_IDERIP 8 /* IDE-R Pin */
83 #define D22IP_MEI2IP 4 /* MEI #2 Pin */
84 #define D22IP_MEI1IP 0 /* MEI #1 Pin */
85 #define D20IP 0x3128 /* 32bit */
86 #define D20IP_XHCI 0 /* XHCI Pin */
87 #define D31IR 0x3140 /* 16bit */
88 #define D30IR 0x3142 /* 16bit */
89 #define D29IR 0x3144 /* 16bit */
90 #define D28IR 0x3146 /* 16bit */
91 #define D27IR 0x3148 /* 16bit */
92 #define D26IR 0x314c /* 16bit */
93 #define D25IR 0x3150 /* 16bit */
94 #define D23IR 0x3158 /* 16bit */
95 #define D22IR 0x315c /* 16bit */
96 #define D20IR 0x3160 /* 16bit */
97 #define D21IR 0x3164 /* 16bit */
98 #define D19IR 0x3168 /* 16bit */
99 #define ACPIIRQEN 0x31e0 /* 32bit */
100 #define OIC 0x31fe /* 16bit */
101 #define DEEP_S3_POL 0x3328 /* 32bit */
102 #define DEEP_S3_EN_AC (1 << 0)
103 #define DEEP_S3_EN_DC (1 << 1)
104 #define DEEP_S5_POL 0x3330 /* 32bit */
105 #define DEEP_S5_EN_AC (1 << 14)
106 #define DEEP_S5_EN_DC (1 << 15)
107 #define DEEP_SX_CONFIG 0x3334 /* 32bit */
108 #define DEEP_SX_WAKE_PIN_EN (1 << 2)
109 #define DEEP_SX_ACPRESENT_PD (1 << 1)
110 #define DEEP_SX_GP27_PIN_EN (1 << 0)
111 #define PMSYNC_CONFIG 0x33c4 /* 32bit */
112 #define PMSYNC_CONFIG2 0x33cc /* 32bit */
113 #define SOFT_RESET_CTRL 0x38f4
114 #define SOFT_RESET_DATA 0x38f8
115 
116 #define DIR_ROUTE(a, b, c, d) \
117  (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
118  ((b) << DIR_IBR) | ((a) << DIR_IAR))
119 
120 #define RC 0x3400 /* 32bit */
121 #define HPTC 0x3404 /* 32bit */
122 #define GCS 0x3410 /* 32bit */
123 #define BUC 0x3414 /* 32bit */
124 #define PCH_DISABLE_GBE (1 << 5)
125 #define FD 0x3418 /* 32bit */
126 #define FDSW 0x3420 /* 8bit */
127 #define DISPBDF 0x3424 /* 16bit */
128 #define FD2 0x3428 /* 32bit */
129 #define CG 0x341c /* 32bit */
130 
131 /* Function Disable 1 RCBA 0x3418 */
132 #define PCH_DISABLE_ALWAYS (1 << 0)
133 #define PCH_DISABLE_ADSPD (1 << 1)
134 #define PCH_DISABLE_SATA1 (1 << 2)
135 #define PCH_DISABLE_SMBUS (1 << 3)
136 #define PCH_DISABLE_HD_AUDIO (1 << 4)
137 #define PCH_DISABLE_EHCI2 (1 << 13)
138 #define PCH_DISABLE_LPC (1 << 14)
139 #define PCH_DISABLE_EHCI1 (1 << 15)
140 #define PCH_DISABLE_PCIE(x) (1 << (16 + x))
141 #define PCH_DISABLE_THERMAL (1 << 24)
142 #define PCH_DISABLE_SATA2 (1 << 25)
143 #define PCH_DISABLE_XHCI (1 << 27)
144 
145 /* Function Disable 2 RCBA 0x3428 */
146 #define PCH_DISABLE_KT (1 << 4)
147 #define PCH_DISABLE_IDER (1 << 3)
148 #define PCH_DISABLE_MEI2 (1 << 2)
149 #define PCH_DISABLE_MEI1 (1 << 1)
150 #define PCH_ENABLE_DBDF (1 << 0)
151 
152 #endif