coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
systemagent.h
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _DENVERTON_NS_SYSTEMAGENT_H_
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#define _DENVERTON_NS_SYSTEMAGENT_H_
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#include <soc/iomap.h>
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/* Device 0:0.0 PCI configuration space (Host Bridge) */
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#define PCH_SA_DEV PCI_DEV(0, SA_DEV, SA_FUNC)
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#define MCHBAR 0x48
/* MCH space. */
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#define PCIEXBAR 0x60
/* PCI express space. */
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#define MASK_PCIEXBAR_256M 0xF0000000
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#define MASK_PCIEXBAR_128M 0xF8000000
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#define MASK_PCIEXBAR_64M 0xFC000000
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#define MASK_PCIEXBAR_LENGTH 0x6
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#define SHIFT_PCIEXBAR_LENGTH 0x1
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#define MASK_PCIEXBAR_LENGTH_256M (0x0 << SHIFT_PCIEXBAR_LENGTH)
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#define MASK_PCIEXBAR_LENGTH_128M (0x1 << SHIFT_PCIEXBAR_LENGTH)
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#define MASK_PCIEXBAR_LENGTH_64M (0x2 << SHIFT_PCIEXBAR_LENGTH)
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#define TOUUD_LO 0xa8
/* Top of Upper Usable DRAM - Low */
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#define MASK_TOUUD_LO 0xFFF00000
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#define TOUUD_HI 0xac
/* Top of Upper Usable DRAM - High */
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#define MASK_TOUUD_HI 0x0000007F
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#define TOUUD TOUUD_LO
/* Top of Upper Usable DRAM */
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#define MASK_TOUUD 0x7FFFF00000
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#define TSEGMB 0xb8
/* TSEG base */
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#define MASK_TSEGMB 0xFFF00000
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#define TOLUD 0xbc
/* Top of Low Used Memory */
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#define MASK_TOLUD 0xFFF00000
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#define CAPID0_A 0xe4
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#define VTD_DISABLE (1 << 23)
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/* SideBand B-UNIT */
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#define B_UNIT 3
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/* SideBand C-UNIT */
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#define C_UNIT 8
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/* SideBand D-UNIT */
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#define D_UNIT 1
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/* SideBand P-UNIT */
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#define P_UNIT 4
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/*
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* MCHBAR
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*/
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#define MCH_BASE_SIZE 0x8000
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#define MCH_BMISC 0x6800
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#define MCH_BMISC_SBVDRAM \
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0x08
/* Bit 3: 1 - reads targeting boot vector are routed to DRAM. */
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#define MCH_BMISC_ABSEGINDRAM \
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0x04
/* Bit 2: 1 - reads targeting A/B-segment are routed to DRAM. */
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#define MCH_BMISC_RFSDRAM \
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0x02
/* Bit 1: 1 - reads targeting E-segment are routed to DRAM. */
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#define MCH_BMISC_RESDRAM \
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0x01
/* Bit 0: 1 - reads targeting E-segment are routed to DRAM. */
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#define MCH_VTBAR_OFFSET 0x6c80
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#define MCH_VTBAR_ENABLE_MASK 0x1
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#define MCH_VTBAR_MASK 0x7ffffff000
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#define MCH_BAR_BIOS_RESET_CPL 0x7078
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#define RST_CPL_BIT (1 << 0)
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#define PCODE_INIT_DONE (1 << 8)
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#define MCH_BAR_CORE_EXISTS_MASK 0x7164
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#define MCH_BAR_CORE_DISABLE_MASK 0x7168
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/* Device 0:4.0 PCI configuration space (RAS) */
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/* Device 0:5.0 PCI configuration space (RCEC) */
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/* Top of 32bit usable memory */
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u32
top_of_32bit_ram
(
void
);
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#endif
//_DENVERTON_NS_SYSTEMAGENT_H_
top_of_32bit_ram
u32 top_of_32bit_ram(void)
u32
uint32_t u32
Definition:
stdint.h:51
src
soc
intel
denverton_ns
include
soc
systemagent.h
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