coreboot
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amd_pci_int_types.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef AMD_PCI_INT_TYPES_H
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#define AMD_PCI_INT_TYPES_H
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const
char
*
intr_types
[] = {
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[0x00] =
"INTA#\t"
,
"INTB#\t"
,
"INTC#\t"
,
"INTD#\t"
,
"INTE#\t"
,
"INTF#\t"
,
"INTG#\t"
,
"INTH#\t"
,
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[0x08] =
"Misc\t"
,
"Misc0\t"
,
"Misc1\t"
,
"Misc2\t"
,
"Ser IRQ INTA"
,
"Ser IRQ INTB"
,
"Ser IRQ INTC"
,
"Ser IRQ INTD"
,
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[0x10] =
"SCI\t"
,
"SMBUS0\t"
,
"ASF\t"
,
"HDA\t"
,
"FC\t\t"
,
"GEC\t"
,
"PerMon\t"
,
"SD\t\t"
,
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[0x20] =
"IMC INT0\t"
,
"IMC INT1\t"
,
"IMC INT2\t"
,
"IMC INT3\t"
,
"IMC INT4\t"
,
"IMC INT5\t"
,
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[0x30] =
"Dev18.0 INTA"
,
"Dev18.2 INTB"
,
"Dev19.0 INTA"
,
"Dev19.2 INTB"
,
"Dev22.0 INTA"
,
"Dev22.2 INTB"
,
"Dev20.5 INTC"
,
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[0x7F] =
"RSVD\t"
,
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#if CONFIG(SOUTHBRIDGE_AMD_PI_AVALON)
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[0x40] =
"RSVD\t"
,
"SATA\t"
,
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[0x60] =
"RSVD\t"
,
"RSVD\t"
,
"GPIO\t"
,
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#elif CONFIG(SOUTHBRIDGE_AMD_PI_KERN)
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[0x40] =
"IDE\t"
,
"SATA\t"
,
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[0x50] =
"GPPInt0\t"
,
"GPPInt1\t"
,
"GPPInt2\t"
,
"GPPInt3\t"
,
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[0x62] =
"GPIO\t"
,
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[0x70] =
"I2C0\t"
,
"I2C1\t"
,
"I2C2\t"
,
"I2C3\t"
,
"UART0\t"
,
"UART1\t"
,
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#endif
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};
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#endif
/* AMD_PCI_INT_TYPES_H */
intr_types
const char * intr_types[]
Definition:
amd_pci_int_types.h:6
src
southbridge
amd
pi
hudson
amd_pci_int_types.h
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