coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef BASEBOARD_GPIO_H
4 #define BASEBOARD_GPIO_H
5 
6 #include <soc/gpio.h>
7 
8 /*
9  * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
10  * which is North community
11  */
12 #define EC_SCI_GPI GPE0_DW1_11
13 
14 /* EC SMI */
15 #define EC_SMI_GPI GPIO_49
16 
17 /*
18  * On lidopen/lidclose GPIO_22 from North Community gets toggled and
19  * is used in _PRW to wake up device from sleep. GPIO_22 maps to
20  * group GPIO_GPE_N_31_0 and the pad is configured as SCI with
21  * EDGE_SINGLE and INVERT.
22  */
23 #define GPE_EC_WAKE GPE0_DW1_22
24 
25 /* Write Protect and indication if EC is in RW code. */
26 #define GPIO_PCH_WP GPIO_75
27 #define GPIO_EC_IN_RW GPIO_41
28 /* Determine if board is in final shipping mode. */
29 #define GPIO_SHIP_MODE GPIO_10
30 
31 /* Memory SKU GPIOs. */
32 #define MEM_CONFIG3 GPIO_45
33 #define MEM_CONFIG2 GPIO_38
34 #define MEM_CONFIG1 GPIO_102
35 #define MEM_CONFIG0 GPIO_101
36 
37 /* DMIC_CONFIG_PIN: High for 1-DMIC and low for 4-DMIC's */
38 #define DMIC_CONFIG_PIN GPIO_17
39 
40 #endif /* BASEBOARD_GPIO_H */