coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef BASEBOARD_GPIO_H
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#define BASEBOARD_GPIO_H
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#include <soc/gpio.h>
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/*
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* GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
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* which is North community
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*/
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#define EC_SCI_GPI GPE0_DW1_11
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/* EC SMI */
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#define EC_SMI_GPI GPIO_49
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/*
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* On lidopen/lidclose GPIO_22 from North Community gets toggled and
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* is used in _PRW to wake up device from sleep. GPIO_22 maps to
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* group GPIO_GPE_N_31_0 and the pad is configured as SCI with
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* EDGE_SINGLE and INVERT.
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*/
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#define GPE_EC_WAKE GPE0_DW1_22
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/* Write Protect and indication if EC is in RW code. */
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#define GPIO_PCH_WP GPIO_75
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#define GPIO_EC_IN_RW GPIO_41
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/* Determine if board is in final shipping mode. */
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#define GPIO_SHIP_MODE GPIO_10
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/* Memory SKU GPIOs. */
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#define MEM_CONFIG3 GPIO_45
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#define MEM_CONFIG2 GPIO_38
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#define MEM_CONFIG1 GPIO_102
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#define MEM_CONFIG0 GPIO_101
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/* DMIC_CONFIG_PIN: High for 1-DMIC and low for 4-DMIC's */
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#define DMIC_CONFIG_PIN GPIO_17
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#endif
/* BASEBOARD_GPIO_H */
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baseboard
include
baseboard
gpio.h
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