coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
raminit.h
Go to the documentation of this file.
1
/* SPDX-License-Identifier: GPL-2.0-only */
2
3
#ifndef RAMINIT_H
4
#define RAMINIT_H
5
6
#include <
stdint.h
>
7
8
#define MAX_DIMM_SOCKETS_PER_CHANNEL 4
9
#define MAX_NUM_CHANNELS 2
10
#define MAX_DIMM_SOCKETS (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL)
11
12
struct
mem_controller
{
13
pci_devfn_t
d0
,
d0f1
;
// PCI bus/device/fcns of E7501 memory controller
14
15
// SMBus addresses of DIMM slots for each channel,
16
// in order from closest to MCH to furthest away
17
// 0 == not present
18
uint16_t
channel0
[
MAX_DIMM_SOCKETS_PER_CHANNEL
];
19
uint16_t
channel1
[
MAX_DIMM_SOCKETS_PER_CHANNEL
];
20
};
21
22
void
sdram_initialize
(
void
);
23
24
#endif
/* RAMINIT_H */
MAX_DIMM_SOCKETS_PER_CHANNEL
#define MAX_DIMM_SOCKETS_PER_CHANNEL
Definition:
raminit.h:8
sdram_initialize
void sdram_initialize(void)
Definition:
raminit.c:1692
pci_devfn_t
u32 pci_devfn_t
Definition:
pci_type.h:8
stdint.h
uint16_t
unsigned short uint16_t
Definition:
stdint.h:11
mem_controller
Definition:
raminit.h:12
mem_controller::channel1
uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL]
Definition:
raminit.h:19
mem_controller::d0
pci_devfn_t d0
Definition:
raminit.h:13
mem_controller::d0f1
pci_devfn_t d0f1
Definition:
raminit.h:13
mem_controller::channel0
uint16_t channel0[MAX_DIMM_SOCKETS_PER_CHANNEL]
Definition:
raminit.h:18
src
northbridge
intel
e7505
raminit.h
Generated by
1.9.1