coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
superio.c
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #include <device/device.h>
4 #include <device/pnp.h>
5 #include <superio/conf_mode.h>
6 #include <pc80/keyboard.h>
7 #include "w83627thg.h"
8 
9 static void w83627thg_init(struct device *dev)
10 {
11 
12  if (!dev->enabled)
13  return;
14 
15  switch (dev->path.pnp.device) {
16  case W83627THG_KBC:
18  break;
19  }
20 }
21 
22 static struct device_operations ops = {
24  .set_resources = pnp_set_resources,
25  .enable_resources = pnp_enable_resources,
26  .enable = pnp_enable,
27  .init = w83627thg_init,
28  .ops_pnp_mode = &pnp_conf_mode_8787_aa,
29 };
30 
31 static struct pnp_info pnp_dev_info[] = {
32  { NULL, W83627THG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
33  { NULL, W83627THG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
34  { NULL, W83627THG_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
35  { NULL, W83627THG_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC1, 0x07f8, },
38  0x07ff, 0x07ff, },
40  0x07ff, 0x07fe, },
41  { NULL, W83627THG_GPIO2, },
44  { NULL, W83627THG_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
45 };
46 
47 static void enable_dev(struct device *dev)
48 {
50 }
51 
53  CHIP_NAME("Winbond W83627THG Super I/O")
54  .enable_dev = enable_dev,
55 };
#define ARRAY_SIZE(a)
Definition: helpers.h:12
const struct pnp_mode_ops pnp_conf_mode_8787_aa
Definition: conf_mode.c:202
#define CHIP_NAME(X)
Definition: device.h:32
uint8_t pc_keyboard_init(uint8_t probe_aux)
Definition: keyboard.c:229
#define NO_AUX_DEVICE
Definition: keyboard.h:6
#define PNP_MSC1
Definition: pnp.h:53
#define PNP_IRQ1
Definition: pnp.h:48
#define PNP_DRQ0
Definition: pnp.h:49
#define PNP_EN
Definition: pnp.h:51
#define PNP_IO1
Definition: pnp.h:43
#define PNP_IO0
Definition: pnp.h:42
#define PNP_IRQ0
Definition: pnp.h:47
#define PNP_MSC0
Definition: pnp.h:52
void pnp_enable(struct device *dev)
Definition: pnp_device.c:181
void pnp_read_resources(struct device *dev)
Definition: pnp_device.c:114
void pnp_enable_devices(struct device *base_dev, struct device_operations *ops, unsigned int functions, struct pnp_info *info)
Definition: pnp_device.c:371
void pnp_set_resources(struct device *dev)
Definition: pnp_device.c:157
void pnp_enable_resources(struct device *dev)
Definition: pnp_device.c:173
#define NULL
Definition: stddef.h:19
void(* read_resources)(struct device *dev)
Definition: device.h:39
struct pnp_path pnp
Definition: path.h:117
Definition: device.h:107
struct device_path path
Definition: device.h:115
unsigned int enabled
Definition: device.h:122
Definition: pnp.h:37
unsigned int device
Definition: path.h:59
#define W83627THG_GPIO2
Definition: w83627thg.h:14
#define W83627THG_KBC
Definition: w83627thg.h:12
#define W83627THG_GPIO3
Definition: w83627thg.h:15
#define W83627THG_SP1
Definition: w83627thg.h:10
#define W83627THG_ACPI
Definition: w83627thg.h:16
#define W83627THG_GAME_MIDI_GPIO1
Definition: w83627thg.h:13
#define W83627THG_HWM
Definition: w83627thg.h:17
#define W83627THG_SP2
Definition: w83627thg.h:11
#define W83627THG_PP
Definition: w83627thg.h:9
#define W83627THG_FDC
Definition: w83627thg.h:8
static void enable_dev(struct device *dev)
Definition: superio.c:47
static struct device_operations ops
Definition: superio.c:22
static struct pnp_info pnp_dev_info[]
Definition: superio.c:31
struct chip_operations superio_winbond_w83627thg_ops
Definition: superio.c:52
static void w83627thg_init(struct device *dev)
Definition: superio.c:9