![]() |
coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
|
Go to the source code of this file.
Macros | |
#define | BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1) |
BIOS_SIZE_{1,2,4,8,16}M. More... | |
#define | SPREAD_SPECTRUM 0 |
0 - Disable Spread Spectrum function 1 - Enable Spread Spectrum function More... | |
#define | HPET_TIMER 1 |
#define | SATA_CONTROLLER CIMX_OPTION_ENABLED |
INCHIP Sata Controller. More... | |
#define | SATA_MODE CONFIG_SB800_SATA_MODE |
INCHIP Sata Controller Mode NOTE: DO NOT ALLOW SATA & IDE use same mode. More... | |
#define | IDE_LEGACY_MODE 0 |
INCHIP Sata IDE Controller Mode. More... | |
#define | IDE_NATIVE_MODE 1 |
#define | SATA_IDE_MODE IDE_LEGACY_MODE |
INCHIP Sata IDE Controller Mode NOTE: DO NOT ALLOW SATA & IDE use same mode. More... | |
#define | EXTERNAL_CLOCK 0x00 |
00/10: Reference clock from crystal oscillator via PAD_XTALI and PAD_XTALO More... | |
#define | INTERNAL_CLOCK 0x01 |
01/11: Reference clock from internal clock through CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL More... | |
#define | SATA_CLOCK_SOURCE INTERNAL_CLOCK |
#define | SATA_PORT_MULT_CAP_RESERVED 1 |
1 ON, 0 0FF More... | |
#define | AZALIA_AUTO 0 |
Detect Azalia controller automatically. More... | |
#define | AZALIA_DISABLE 1 |
Disable Azalia controller. More... | |
#define | AZALIA_ENABLE 2 |
Enable Azalia controller. More... | |
#define | AZALIA_CONTROLLER AZALIA_AUTO |
INCHIP HDA controller. More... | |
#define | AZALIA_PIN_CONFIG 1 |
0 - disable 1 - enable More... | |
#define | GPP_CFGMODE GPP_CFGMODE_X1111 |
GPP Link Configuration four possible configuration: GPP_CFGMODE_X4000 GPP_CFGMODE_X2200 GPP_CFGMODE_X2110 GPP_CFGMODE_X1111. More... | |
#define | NB_SB_GEN2 TRUE |
0 - Disable 1 - Enable More... | |
#define | SB_GPP_GEN2 TRUE |
0 - Disable 1 - Enable More... | |
#define | SB_GPP_UNHIDE_PORTS FALSE |
TRUE - ports visible always, even port empty FALSE - ports invisible if port empty. More... | |
#define | GEC_CONFIG 1 |
0 - Enable 1 - Disable More... | |
#define | AZALIA_OEM_VERB_TABLE (&codec_tablelist[0]) |
Mainboard specific codec verb table list. More... | |
Variables | |
static const CODECENTRY | frontrunneraf_codec_alc886 [] |
static const CODECTBLLIST | codec_tablelist [] |
#define AZALIA_AUTO 0 |
Detect Azalia controller automatically.
Definition at line 131 of file platform_cfg.h.
#define AZALIA_CONTROLLER AZALIA_AUTO |
INCHIP HDA controller.
Definition at line 138 of file platform_cfg.h.
#define AZALIA_DISABLE 1 |
Disable Azalia controller.
Definition at line 132 of file platform_cfg.h.
#define AZALIA_ENABLE 2 |
Enable Azalia controller.
Definition at line 133 of file platform_cfg.h.
#define AZALIA_OEM_VERB_TABLE (&codec_tablelist[0]) |
Mainboard specific codec verb table list.
Definition at line 243 of file platform_cfg.h.
#define AZALIA_PIN_CONFIG 1 |
0 - disable 1 - enable
Definition at line 146 of file platform_cfg.h.
#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1) |
BIOS_SIZE_{1,2,4,8,16}M.
In SB800, default ROM size is 1M Bytes, if your platform ROM bigger than 1M you have to set the ROM size outside CIMx module and before AGESA module get call.
Definition at line 16 of file platform_cfg.h.
#define EXTERNAL_CLOCK 0x00 |
00/10: Reference clock from crystal oscillator via PAD_XTALI and PAD_XTALO
Definition at line 106 of file platform_cfg.h.
#define GEC_CONFIG 1 |
0 - Enable 1 - Disable
Definition at line 211 of file platform_cfg.h.
#define GPP_CFGMODE GPP_CFGMODE_X1111 |
GPP Link Configuration four possible configuration: GPP_CFGMODE_X4000 GPP_CFGMODE_X2200 GPP_CFGMODE_X2110 GPP_CFGMODE_X1111.
Definition at line 183 of file platform_cfg.h.
#define HPET_TIMER 1 |
Definition at line 33 of file platform_cfg.h.
#define IDE_LEGACY_MODE 0 |
INCHIP Sata IDE Controller Mode.
Definition at line 87 of file platform_cfg.h.
#define IDE_NATIVE_MODE 1 |
Definition at line 88 of file platform_cfg.h.
#define INTERNAL_CLOCK 0x01 |
01/11: Reference clock from internal clock through CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
Definition at line 107 of file platform_cfg.h.
#define NB_SB_GEN2 TRUE |
0 - Disable 1 - Enable
Definition at line 190 of file platform_cfg.h.
#define SATA_CLOCK_SOURCE INTERNAL_CLOCK |
Definition at line 112 of file platform_cfg.h.
#define SATA_CONTROLLER CIMX_OPTION_ENABLED |
INCHIP Sata Controller.
Definition at line 75 of file platform_cfg.h.
#define SATA_IDE_MODE IDE_LEGACY_MODE |
INCHIP Sata IDE Controller Mode NOTE: DO NOT ALLOW SATA & IDE use same mode.
Definition at line 95 of file platform_cfg.h.
#define SATA_MODE CONFIG_SB800_SATA_MODE |
INCHIP Sata Controller Mode NOTE: DO NOT ALLOW SATA & IDE use same mode.
Definition at line 82 of file platform_cfg.h.
#define SATA_PORT_MULT_CAP_RESERVED 1 |
1 ON, 0 0FF
Definition at line 118 of file platform_cfg.h.
#define SB_GPP_GEN2 TRUE |
0 - Disable 1 - Enable
Definition at line 197 of file platform_cfg.h.
#define SB_GPP_UNHIDE_PORTS FALSE |
TRUE - ports visible always, even port empty FALSE - ports invisible if port empty.
Definition at line 204 of file platform_cfg.h.
#define SPREAD_SPECTRUM 0 |
0 - Disable Spread Spectrum function 1 - Enable Spread Spectrum function
Definition at line 25 of file platform_cfg.h.
|
static |
Definition at line 233 of file platform_cfg.h.
|
static |
Definition at line 213 of file platform_cfg.h.