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pci_def.h
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#ifndef PCI_DEF_H
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#define PCI_DEF_H
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/*
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* Under PCI, each device has 256 bytes of configuration address space,
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* of which the first 64 bytes are standardized as follows:
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*/
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#define PCI_VENDOR_ID 0x00
/* 16 bits */
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#define PCI_DEVICE_ID 0x02
/* 16 bits */
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#define PCI_COMMAND 0x04
/* 16 bits */
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#define PCI_COMMAND_IO 0x1
/* Enable response in I/O space */
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#define PCI_COMMAND_MEMORY 0x2
/* Enable response in Memory space */
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#define PCI_COMMAND_MASTER 0x4
/* Enable bus mastering */
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#define PCI_COMMAND_SPECIAL 0x8
/* Enable response to special cycles */
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#define PCI_COMMAND_INVALIDATE 0x10
/* Use memory write and invalidate */
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#define PCI_COMMAND_VGA_PALETTE 0x20
/* Enable palette snooping */
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#define PCI_COMMAND_PARITY 0x40
/* Enable parity checking */
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#define PCI_COMMAND_WAIT 0x80
/* Enable address/data stepping */
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#define PCI_COMMAND_SERR 0x100
/* Enable SERR */
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#define PCI_COMMAND_FAST_BACK 0x200
/* Enable back-to-back writes */
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#define PCI_COMMAND_INT_DISABLE 0x400
/* Interrupt disable */
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#define PCI_STATUS 0x06
/* 16 bits */
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#define PCI_STATUS_CAP_LIST 0x10
/* Support Capability List */
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#define PCI_STATUS_66MHZ 0x20
/* Support 66 Mhz PCI 2.1 bus */
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/* Support User Definable Features [obsolete] */
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#define PCI_STATUS_UDF 0x40
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#define PCI_STATUS_FAST_BACK 0x80
/* Accept fast-back to back */
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#define PCI_STATUS_PARITY 0x100
/* Detected parity error */
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#define PCI_STATUS_DEVSEL_MASK 0x600
/* DEVSEL timing */
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#define PCI_STATUS_DEVSEL_FAST 0x000
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#define PCI_STATUS_DEVSEL_MEDIUM 0x200
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#define PCI_STATUS_DEVSEL_SLOW 0x400
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#define PCI_STATUS_SIG_TARGET_ABORT 0x800
/* Set on target abort */
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#define PCI_STATUS_REC_TARGET_ABORT 0x1000
/* Master ack of " */
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#define PCI_STATUS_REC_MASTER_ABORT 0x2000
/* Set on master abort */
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#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000
/* Set when we drive SERR */
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#define PCI_STATUS_DETECTED_PARITY 0x8000
/* Set on parity error */
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#define PCI_CLASS_REVISION 0x08
/* High 24 bits are class, low 8
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revision */
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#define PCI_REVISION_ID 0x08
/* Revision ID */
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#define PCI_CLASS_PROG 0x09
/* Reg. Level Programming Interface */
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#define PCI_CLASS_DEVICE 0x0a
/* Device class */
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#define PCI_CACHE_LINE_SIZE 0x0c
/* 8 bits */
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#define PCI_LATENCY_TIMER 0x0d
/* 8 bits */
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#define PCI_HEADER_TYPE 0x0e
/* 8 bits */
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#define PCI_HEADER_TYPE_NORMAL 0
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#define PCI_HEADER_TYPE_BRIDGE 1
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#define PCI_HEADER_TYPE_CARDBUS 2
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#define PCI_BIST 0x0f
/* 8 bits */
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#define PCI_BIST_CODE_MASK 0x0f
/* Return result */
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#define PCI_BIST_START 0x40
/* 1 to start BIST, 2 secs or less */
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#define PCI_BIST_CAPABLE 0x80
/* 1 if BIST capable */
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/*
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* Base addresses specify locations in memory or I/O space.
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* Decoded size can be determined by writing a value of
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* 0xffffffff to the register, and reading it back. Only
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* 1 bits are decoded.
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*/
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#define PCI_BASE_ADDRESS_0 0x10
/* 32 bits */
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#define PCI_BASE_ADDRESS_1 0x14
/* 32 bits [htype 0,1 only] */
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#define PCI_BASE_ADDRESS_2 0x18
/* 32 bits [htype 0 only] */
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#define PCI_BASE_ADDRESS_3 0x1c
/* 32 bits */
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#define PCI_BASE_ADDRESS_4 0x20
/* 32 bits */
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#define PCI_BASE_ADDRESS_5 0x24
/* 32 bits */
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#define PCI_BASE_ADDRESS_SPACE 0x01
/* 0 = memory, 1 = I/O */
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#define PCI_BASE_ADDRESS_SPACE_IO 0x01
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#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
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#define PCI_BASE_ADDRESS_MEM_LIMIT_MASK 0x06
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#define PCI_BASE_ADDRESS_MEM_LIMIT_32 0x00
/* 32 bit address */
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#define PCI_BASE_ADDRESS_MEM_LIMIT_1M 0x02
/* Below 1M [obsolete] */
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#define PCI_BASE_ADDRESS_MEM_LIMIT_64 0x04
/* 64 bit address */
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#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08
/* prefetchable? */
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#define PCI_BASE_ADDRESS_MEM_ATTR_MASK 0x0f
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#define PCI_BASE_ADDRESS_IO_ATTR_MASK 0x03
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/* bit 1 is reserved if address_space = 1 */
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/* Header type 0 (normal devices) */
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#define PCI_CARDBUS_CIS 0x28
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#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
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#define PCI_SUBSYSTEM_ID 0x2e
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/* Bits 31..11 are address, 10..1 reserved */
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#define PCI_ROM_ADDRESS 0x30
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#define PCI_ROM_ADDRESS_ENABLE 0x01
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#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
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/* Offset of first capability list entry */
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#define PCI_CAPABILITY_LIST 0x34
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/* 0x35-0x3b are reserved */
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#define PCI_INTERRUPT_LINE 0x3c
/* 8 bits */
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#define PCI_INTERRUPT_PIN 0x3d
/* 8 bits */
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#define PCI_MIN_GNT 0x3e
/* 8 bits */
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#define PCI_MAX_LAT 0x3f
/* 8 bits */
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/* Header type 1 (PCI-to-PCI bridges) */
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#define PCI_PRIMARY_BUS 0x18
/* Primary bus number */
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#define PCI_SECONDARY_BUS 0x19
/* Secondary bus number */
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/* Highest bus number behind the bridge */
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#define PCI_SUBORDINATE_BUS 0x1a
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/* Latency timer for secondary interface */
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#define PCI_SEC_LATENCY_TIMER 0x1b
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#define PCI_IO_BASE 0x1c
/* I/O range behind the bridge */
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#define PCI_IO_LIMIT 0x1d
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#define PCI_IO_RANGE_TYPE_MASK 0x0f
/* I/O bridging type */
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#define PCI_IO_RANGE_TYPE_16 0x00
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#define PCI_IO_RANGE_TYPE_32 0x01
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#define PCI_IO_RANGE_MASK ~0x0f
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/* Secondary status register, only bit 14 used */
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#define PCI_SEC_STATUS 0x1e
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#define PCI_MEMORY_BASE 0x20
/* Memory range behind */
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#define PCI_MEMORY_LIMIT 0x22
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#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
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#define PCI_MEMORY_RANGE_MASK ~0x0f
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#define PCI_PREF_MEMORY_BASE 0x24
/* Prefetchable memory range behind */
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#define PCI_PREF_MEMORY_LIMIT 0x26
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#define PCI_PREF_RANGE_TYPE_MASK 0x0f
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#define PCI_PREF_RANGE_TYPE_32 0x00
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#define PCI_PREF_RANGE_TYPE_64 0x01
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#define PCI_PREF_RANGE_MASK ~0x0f
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/* Upper half of prefetchable memory range */
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#define PCI_PREF_BASE_UPPER32 0x28
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#define PCI_PREF_LIMIT_UPPER32 0x2c
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#define PCI_IO_BASE_UPPER16 0x30
/* Upper half of I/O addresses */
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#define PCI_IO_LIMIT_UPPER16 0x32
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/* 0x34 same as for htype 0 */
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/* 0x35-0x3b is reserved */
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/* Same as PCI_ROM_ADDRESS, but for htype 1 */
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#define PCI_ROM_ADDRESS1 0x38
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/* 0x3c-0x3d are same as for htype 0 */
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#define PCI_BRIDGE_CONTROL 0x3e
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/* Enable parity detection on secondary interface */
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#define PCI_BRIDGE_CTL_PARITY 0x01
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#define PCI_BRIDGE_CTL_SERR 0x02
/* The same for SERR forwarding */
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#define PCI_BRIDGE_CTL_ISA 0x04
/* Disable bridging of ISA ports */
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#define PCI_BRIDGE_CTL_VGA 0x08
/* Forward VGA addresses */
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#define PCI_BRIDGE_CTL_VGA16 0x10
/* Enable 16-bit i/o port decoding */
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#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20
/* Report master aborts */
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#define PCI_BRIDGE_CTL_BUS_RESET 0x40
/* Secondary bus reset */
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/* Fast Back2Back enabled on secondary interface */
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#define PCI_BRIDGE_CTL_FAST_BACK 0x80
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/* Header type 2 (CardBus bridges) */
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#define PCI_CB_CAPABILITY_LIST 0x14
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/* 0x15 reserved */
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#define PCI_CB_SEC_STATUS 0x16
/* Secondary status */
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#define PCI_CB_PRIMARY_BUS 0x18
/* PCI bus number */
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#define PCI_CB_CARD_BUS 0x19
/* CardBus bus number */
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#define PCI_CB_SUBORDINATE_BUS 0x1a
/* Subordinate bus number */
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#define PCI_CB_LATENCY_TIMER 0x1b
/* CardBus latency timer */
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#define PCI_CB_MEMORY_BASE_0 0x1c
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#define PCI_CB_MEMORY_LIMIT_0 0x20
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#define PCI_CB_MEMORY_BASE_1 0x24
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#define PCI_CB_MEMORY_LIMIT_1 0x28
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#define PCI_CB_IO_BASE_0 0x2c
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#define PCI_CB_IO_BASE_0_HI 0x2e
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#define PCI_CB_IO_LIMIT_0 0x30
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#define PCI_CB_IO_LIMIT_0_HI 0x32
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#define PCI_CB_IO_BASE_1 0x34
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#define PCI_CB_IO_BASE_1_HI 0x36
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#define PCI_CB_IO_LIMIT_1 0x38
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#define PCI_CB_IO_LIMIT_1_HI 0x3a
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#define PCI_CB_IO_RANGE_MASK ~0x03
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/* 0x3c-0x3d are same as for htype 0 */
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#define PCI_CB_BRIDGE_CONTROL 0x3e
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/* Similar to standard bridge control register */
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#define PCI_CB_BRIDGE_CTL_PARITY 0x01
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#define PCI_CB_BRIDGE_CTL_SERR 0x02
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#define PCI_CB_BRIDGE_CTL_ISA 0x04
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#define PCI_CB_BRIDGE_CTL_VGA 0x08
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#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
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#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40
/* CardBus reset */
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/* Enable interrupt for 16-bit cards */
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#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80
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/* Prefetch enable for both memory regions */
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#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100
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#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
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#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
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#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
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#define PCI_CB_SUBSYSTEM_ID 0x42
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/* 16-bit PC Card legacy mode base address (ExCa) */
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#define PCI_CB_LEGACY_MODE_BASE 0x44
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/* 0x48-0x7f reserved */
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/* Capability lists */
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#define PCI_CAP_LIST_ID 0
/* Capability ID */
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#define PCI_CAP_ID_PM 0x01
/* Power Management */
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#define PCI_CAP_ID_AGP 0x02
/* Accelerated Graphics Port */
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#define PCI_CAP_ID_VPD 0x03
/* Vital Product Data */
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#define PCI_CAP_ID_SLOTID 0x04
/* Slot Identification */
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#define PCI_CAP_ID_MSI 0x05
/* Message Signaled Interrupts */
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#define PCI_CAP_ID_CHSWP 0x06
/* CompactPCI HotSwap */
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#define PCI_CAP_ID_PCIX 0x07
/* PCIX */
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#define PCI_CAP_ID_HT 0x08
/* Hypertransport */
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#define PCI_CAP_ID_EHCI_DEBUG 0x0A
/* EHCI debug port */
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#define PCI_CAP_ID_SHPC 0x0C
/* PCI Standard Hot-Plug Controller */
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#define PCI_CAP_ID_SSVID 0x0D
/* Bridge subsystem vendor/device ID */
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#define PCI_CAP_ID_PCIE 0x10
/* PCI Express */
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#define PCI_CAP_ID_MSIX 0x11
/* MSI-X */
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#define PCI_CAP_LIST_NEXT 1
/* Next capability in the list */
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#define PCI_CAP_FLAGS 2
/* Capability defined flags (16 bits) */
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/* Hypertransport Registers */
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#define PCI_HT_CAP_SIZEOF 4
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#define PCI_HT_CAP_HOST_CTRL 4
/* Host link control */
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#define PCI_HT_CAP_HOST_WIDTH 6
/* width value & capability */
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#define PCI_HT_CAP_HOST_FREQ 0x09
/* Host frequency */
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#define PCI_HT_CAP_HOST_FREQ_CAP 0x0a
/* Host Frequency capability */
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#define PCI_HT_CAP_SLAVE_CTRL0 4
/* link control */
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#define PCI_HT_CAP_SLAVE_CTRL1 8
/* link control to */
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#define PCI_HT_CAP_SLAVE_WIDTH0 6
/* width value & capability */
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#define PCI_HT_CAP_SLAVE_WIDTH1 0x0a
/* width value & capability to */
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#define PCI_HT_CAP_SLAVE_FREQ0 0x0d
/* Slave frequency from */
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#define PCI_HT_CAP_SLAVE_FREQ1 0x011
/* Slave frequency to */
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#define PCI_HT_CAP_SLAVE_FREQ_CAP0 0x0e
/* Frequency capability from */
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#define PCI_HT_CAP_SLAVE_FREQ_CAP1 0x12
/* Frequency capability to */
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#define PCI_HT_CAP_SLAVE_LINK_ENUM 0x14
/* Link Enumeration Scratchpad */
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/* Power Management Registers */
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#define PCI_PM_PMC 2
/* PM Capabilities Register */
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#define PCI_PM_CAP_VER_MASK 0x0007
/* Version */
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#define PCI_PM_CAP_PME_CLOCK 0x0008
/* PME clock required */
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#define PCI_PM_CAP_AUX_POWER 0x0010
/* Auxiliary power support */
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#define PCI_PM_CAP_DSI 0x0020
/* Device specific initialization */
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#define PCI_PM_CAP_D1 0x0200
/* D1 power state support */
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#define PCI_PM_CAP_D2 0x0400
/* D2 power state support */
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#define PCI_PM_CAP_PME 0x0800
/* PME pin supported */
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#define PCI_PM_CTRL 4
/* PM control and status register */
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#define PCI_PM_CTRL_STATE_MASK 0x0003
/* Current power state (D0 to D3) */
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#define PCI_PM_CTRL_POWER_STATE_D0 0x0
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#define PCI_PM_CTRL_POWER_STATE_D1 0x1
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#define PCI_PM_CTRL_POWER_STATE_D2 0x2
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#define PCI_PM_CTRL_POWER_STATE_D3HOT 0x3
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#define PCI_PM_CTRL_PME_ENABLE 0x0100
/* PME pin enable */
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#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00
/* Data select (??) */
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#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000
/* Data scale (??) */
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#define PCI_PM_CTRL_PME_STATUS 0x8000
/* PME pin status */
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#define PCI_PM_PPB_EXTENSIONS 6
/* PPB support extensions (??) */
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#define PCI_PM_PPB_B2_B3 0x40
/* Stop clock when in D3hot (??) */
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/* Bus power/clock control enable (??) */
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#define PCI_PM_BPCC_ENABLE 0x80
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#define PCI_PM_DATA_REGISTER 7
/* (??) */
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#define PCI_PM_SIZEOF 8
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/* AGP registers */
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#define PCI_AGP_VERSION 2
/* BCD version number */
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#define PCI_AGP_RFU 3
/* Rest of capability flags */
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#define PCI_AGP_STATUS 4
/* Status register */
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/* Maximum number of requests - 1 */
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#define PCI_AGP_STATUS_RQ_MASK 0xff000000
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#define PCI_AGP_STATUS_SBA 0x0200
/* Sideband addressing supported */
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#define PCI_AGP_STATUS_64BIT 0x0020
/* 64-bit addressing supported */
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#define PCI_AGP_STATUS_FW 0x0010
/* FW transfers supported */
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#define PCI_AGP_STATUS_RATE4 0x0004
/* 4x transfer rate supported */
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#define PCI_AGP_STATUS_RATE2 0x0002
/* 2x transfer rate supported */
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#define PCI_AGP_STATUS_RATE1 0x0001
/* 1x transfer rate supported */
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#define PCI_AGP_COMMAND 8
/* Control register */
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/* Master: Maximum number of requests */
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#define PCI_AGP_COMMAND_RQ_MASK 0xff000000
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#define PCI_AGP_COMMAND_SBA 0x0200
/* Sideband addressing enabled */
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/* Allow processing of AGP transactions */
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#define PCI_AGP_COMMAND_AGP 0x0100
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/* Allow processing of 64-bit addresses */
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#define PCI_AGP_COMMAND_64BIT 0x0020
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#define PCI_AGP_COMMAND_FW 0x0010
/* Force FW transfers */
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#define PCI_AGP_COMMAND_RATE4 0x0004
/* Use 4x rate */
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#define PCI_AGP_COMMAND_RATE2 0x0002
/* Use 4x rate */
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#define PCI_AGP_COMMAND_RATE1 0x0001
/* Use 4x rate */
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#define PCI_AGP_SIZEOF 12
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/* Slot Identification */
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#define PCI_SID_ESR 2
/* Expansion Slot Register */
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/* Number of expansion slots available */
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#define PCI_SID_ESR_NSLOTS 0x1f
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#define PCI_SID_ESR_FIC 0x20
/* First In Chassis Flag */
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#define PCI_SID_CHASSIS_NR 3
/* Chassis Number */
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/* Message Signaled Interrupts registers */
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#define PCI_MSI_FLAGS 2
/* Various flags */
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#define PCI_MSI_FLAGS_64BIT 0x80
/* 64-bit addresses allowed */
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#define PCI_MSI_FLAGS_QSIZE 0x70
/* Message queue size configured */
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#define PCI_MSI_FLAGS_QMASK 0x0e
/* Maximum queue size available */
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#define PCI_MSI_FLAGS_ENABLE 0x01
/* MSI feature enabled */
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#define PCI_MSI_RFU 3
/* Rest of capability flags */
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#define PCI_MSI_ADDRESS_LO 4
/* Lower 32 bits */
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/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
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#define PCI_MSI_ADDRESS_HI 8
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#define PCI_MSI_DATA_32 8
/* 16 bits of data for 32-bit devices */
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#define PCI_MSI_DATA_64 12
/* 16 bits of data for 64-bit devices */
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#define PCI_MSI_MASK_BIT 16
/* Mask bits register */
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/* MSI-X registers */
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#define PCI_MSIX_FLAGS 2
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#define PCI_MSIX_FLAGS_QSIZE 0x7FF
/* table size */
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#define PCI_MSIX_FLAGS_MASKALL 0x4000
/* Mask all vectors for this function */
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#define PCI_MSIX_FLAGS_ENABLE 0x8000
/* MSI-X enable */
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#define PCI_MSIX_TABLE 4
/* Table offset */
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#define PCI_MSIX_PBA 8
/* Pending Bit Array offset */
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#define PCI_MSIX_PBA_BIR 0x7
/* BAR index */
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#define PCI_MSIX_PBA_OFFSET ~0x7
/* Offset into specified BAR */
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#define PCI_CAP_MSIX_SIZEOF 12
/* size of MSIX registers */
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/* CompactPCI Hotswap Register */
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#define PCI_CHSWP_CSR 2
/* Control and Status Register */
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#define PCI_CHSWP_DHA 0x01
/* Device Hiding Arm */
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#define PCI_CHSWP_EIM 0x02
/* ENUM# Signal Mask */
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#define PCI_CHSWP_PIE 0x04
/* Pending Insert or Extract */
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#define PCI_CHSWP_LOO 0x08
/* LED On / Off */
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#define PCI_CHSWP_PI 0x30
/* Programming Interface */
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#define PCI_CHSWP_EXT 0x40
/* ENUM# status - extraction */
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#define PCI_CHSWP_INS 0x80
/* ENUM# status - insertion */
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/* PCI-X registers */
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#define PCI_X_CMD 2
/* Modes & Features */
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#define PCI_X_CMD_DPERR_E 0x0001
/* Data Parity Error Recovery Enable */
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#define PCI_X_CMD_ERO 0x0002
/* Enable Relaxed Ordering */
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#define PCI_X_CMD_MAX_READ 0x000c
/* Max Memory Read Byte Count */
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#define PCI_X_CMD_MAX_SPLIT 0x0070
/* Max Outstanding Split Transactions */
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#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3)
/* Version */
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#define PCI_X_STATUS 4
/* PCI-X capabilities */
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#define PCI_X_STATUS_DEVFN 0x000000ff
/* A copy of devfn */
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#define PCI_X_STATUS_BUS 0x0000ff00
/* A copy of bus nr */
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#define PCI_X_STATUS_64BIT 0x00010000
/* 64-bit device */
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#define PCI_X_STATUS_133MHZ 0x00020000
/* 133 MHz capable */
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#define PCI_X_STATUS_SPL_DISC 0x00040000
/* Split Completion Discarded */
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/* Unexpected Split Completion */
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#define PCI_X_STATUS_UNX_SPL 0x00080000
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#define PCI_X_STATUS_COMPLEX 0x00100000
/* Device Complexity */
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/* Designed Max Memory Read Count */
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#define PCI_X_STATUS_MAX_READ 0x00600000
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/* Designed Max Cumulative Read Size */
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#define PCI_X_STATUS_MAX_SPLIT 0x03800000
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/* Rcvd Split Completion Error Msg */
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#define PCI_X_STATUS_SPL_ERR 0x20000000
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#define PCI_X_STATUS_266MHZ 0x40000000
/* 266 MHz capable */
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#define PCI_X_STATUS_533MHZ 0x80000000
/* 533 MHz capable */
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/* PCI-X bridge registers */
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#define PCI_X_SEC_STATUS 2
/* Secondary status */
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/* The bus behind the bridge is 64bits wide */
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#define PCI_X_SSTATUS_64BIT 0x0001
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/* The bus behind the bridge is 133Mhz Capable */
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#define PCI_X_SSTATUS_133MHZ 0x0002
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#define PCI_X_SSTATUS_SPL_DISC 0x0004
/* Split Completion Discarded */
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#define PCI_X_SSTATUS_UNX_SPL 0x0008
/* Unexpected Split Completion */
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#define PCI_X_SSTATUS_SPL_OVR 0x0010
/* Split Completion Overrun */
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#define PCI_X_SSTATUS_SPL_DLY 0x0020
/* Split Completion Delayed */
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/* PCI-X mode and frequency */
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#define PCI_X_SSTATUS_MFREQ(x) (((x) & 0x03c0) >> 6)
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#define PCI_X_SSTATUS_CONVENTIONAL_PCI 0x0
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#define PCI_X_SSTATUS_MODE1_66MHZ 0x1
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#define PCI_X_SSTATUS_MODE1_100MHZ 0x2
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#define PCI_X_SSTATUS_MODE1_133MHZ 0x3
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#define PCI_X_SSTATUS_MODE2_266MHZ_REF_66MHZ 0x9
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#define PCI_X_SSTATUS_MODE2_266MHZ_REF_100MHZ 0xa
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#define PCI_X_SSTATUS_MODE2_266MHZ_REF_133MHZ 0xb
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#define PCI_X_SSTATUS_MODE2_533MHZ_REF_66MHZ 0xd
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#define PCI_X_SSTATUS_MODE2_533MHZ_REF_100MHZ 0xe
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#define PCI_X_SSTATUS_MODE2_533MHZ_REF_133MHZ 0xf
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#define PCI_X_SSTATUS_VERSION(x) (((x) >> 12) & 3)
/* Version */
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/* The bus behind the bridge is 266Mhz Capable */
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#define PCI_X_SSTATUS_266MHZ 0x4000
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/* The bus behind the bridge is 533Mhz Capable */
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#define PCI_X_SSTAUTS_533MHZ 0x8000
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/* PCI Express capability registers */
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#define PCI_EXP_FLAGS 2
/* Capabilities register */
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#define PCI_EXP_FLAGS_VERS 0x000f
/* Capability version */
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#define PCI_EXP_FLAGS_TYPE 0x00f0
/* Device/Port type */
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#define PCI_EXP_TYPE_ENDPOINT 0x0
/* Express Endpoint */
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#define PCI_EXP_TYPE_LEG_END 0x1
/* Legacy Endpoint */
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#define PCI_EXP_TYPE_ROOT_PORT 0x4
/* Root Port */
385
#define PCI_EXP_TYPE_UPSTREAM 0x5
/* Upstream Port */
386
#define PCI_EXP_TYPE_DOWNSTREAM 0x6
/* Downstream Port */
387
#define PCI_EXP_TYPE_PCI_BRIDGE 0x7
/* PCI/PCI-X Bridge */
388
#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8
/* PCI/PCI-X to PCIe Bridge */
389
#define PCI_EXP_FLAGS_SLOT 0x0100
/* Slot implemented */
390
#define PCI_EXP_FLAGS_IRQ 0x3e00
/* Interrupt message number */
391
#define PCI_EXP_DEVCAP 4
/* Device capabilities */
392
#define PCI_EXP_DEVCAP_PAYLOAD 0x07
/* Max_Payload_Size */
393
#define PCI_EXP_DEVCAP_PHANTOM 0x18
/* Phantom functions */
394
#define PCI_EXP_DEVCAP_EXT_TAG 0x20
/* Extended tags */
395
#define PCI_EXP_DEVCAP_L0S 0x1c0
/* L0s Acceptable Latency */
396
#define PCI_EXP_DEVCAP_L1 0xe00
/* L1 Acceptable Latency */
397
#define PCI_EXP_DEVCAP_ATN_BUT 0x1000
/* Attention Button Present */
398
#define PCI_EXP_DEVCAP_ATN_IND 0x2000
/* Attention Indicator Present */
399
#define PCI_EXP_DEVCAP_PWR_IND 0x4000
/* Power Indicator Present */
400
#define PCI_EXP_DEVCAP_RBER 0x8000
/* Role-Based Error Reporting */
401
#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000
/* Slot Power Limit Value */
402
#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000
/* Slot Power Limit Scale */
403
#define PCI_EXP_DEVCTL 8
/* Device Control */
404
#define PCI_EXP_DEVCTL_CERE 0x0001
/* Correctable Error Reporting En. */
405
#define PCI_EXP_DEVCTL_NFERE 0x0002
/* Non-Fatal Error Reporting Enable */
406
#define PCI_EXP_DEVCTL_FERE 0x0004
/* Fatal Error Reporting Enable */
407
#define PCI_EXP_DEVCTL_URRE 0x0008
/* Unsupported Request Reporting En. */
408
#define PCI_EXP_DEVCTL_RELAX_EN 0x0010
/* Enable relaxed ordering */
409
#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0
/* Max_Payload_Size */
410
#define PCI_EXP_DEVCTL_EXT_TAG 0x0100
/* Extended Tag Field Enable */
411
#define PCI_EXP_DEVCTL_PHANTOM 0x0200
/* Phantom Functions Enable */
412
#define PCI_EXP_DEVCTL_AUX_PME 0x0400
/* Auxiliary Power PM Enable */
413
#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800
/* Enable No Snoop */
414
#define PCI_EXP_DEVCTL_READRQ 0x7000
/* Max_Read_Request_Size */
415
#define PCI_EXP_DEVSTA 10
/* Device Status */
416
#define PCI_EXP_DEVSTA_CED 0x01
/* Correctable Error Detected */
417
#define PCI_EXP_DEVSTA_NFED 0x02
/* Non-Fatal Error Detected */
418
#define PCI_EXP_DEVSTA_FED 0x04
/* Fatal Error Detected */
419
#define PCI_EXP_DEVSTA_URD 0x08
/* Unsupported Request Detected */
420
#define PCI_EXP_DEVSTA_AUXPD 0x10
/* AUX Power Detected */
421
#define PCI_EXP_DEVSTA_TRPND 0x20
/* Transactions Pending */
422
#define PCI_EXP_LNKCAP 12
/* Link Capabilities */
423
#define PCI_EXP_LNKCAP_ASPMS 0xc00
/* ASPM Support */
424
#define PCI_EXP_LNKCAP_L0SEL 0x7000
/* L0s Exit Latency */
425
#define PCI_EXP_LNKCAP_L1EL 0x38000
/* L1 Exit Latency */
426
#define PCI_EXP_CLK_PM 0x40000
/* Clock Power Management */
427
#define PCI_EXP_LNKCAP_PORT 0xff000000
/* Port Number */
428
#define PCI_EXP_LNKCTL 16
/* Link Control */
429
#define PCI_EXP_LNKCTL_RL 0x20
/* Retrain Link */
430
#define PCI_EXP_LNKCTL_CCC 0x40
/* Common Clock COnfiguration */
431
#define PCI_EXP_EN_CLK_PM 0x100
/* Enable Clock Power Management */
432
#define PCI_EXP_LNKSTA 18
/* Link Status */
433
#define PCI_EXP_LNKSTA_LT 0x800
/* Link Training */
434
#define PCI_EXP_LNKSTA_SLC 0x1000
/* Slot Clock Configuration */
435
#define PCI_EXP_SLTCAP 20
/* Slot Capabilities */
436
#define PCI_EXP_SLTCAP_HPC 0x0040
/* Hot-Plug Capable */
437
#define PCI_EXP_SLTCTL 24
/* Slot Control */
438
#define PCI_EXP_SLTSTA 26
/* Slot Status */
439
#define PCI_EXP_RTCTL 28
/* Root Control */
440
#define PCI_EXP_RTCTL_SECEE 0x01
/* System Error on Correctable Error */
441
#define PCI_EXP_RTCTL_SENFEE 0x02
/* System Error on Non-Fatal Error */
442
#define PCI_EXP_RTCTL_SEFEE 0x04
/* System Error on Fatal Error */
443
#define PCI_EXP_RTCTL_PMEIE 0x08
/* PME Interrupt Enable */
444
#define PCI_EXP_RTCTL_CRSSVE 0x10
/* CRS Software Visibility Enable */
445
#define PCI_EXP_RTCAP 30
/* Root Capabilities */
446
#define PCI_EXP_RTSTA 32
/* Root Status */
447
#define PCI_EXP_DEVCAP2 36
/* Device capabilities 2 */
448
#define PCI_EXP_DEVCAP2_LTR 0x0800
/* LTR supported */
449
#define PCI_EXP_DEVCTL2 40
/* Device Control 2 */
450
#define PCI_EXP_DEV2_LTR 0x0400
/* LTR enabled */
451
452
/* Extended Capabilities (PCI-X 2.0 and Express) */
453
#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
454
#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
455
#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
456
457
#define PCI_EXT_CAP_ID_ERR 1
458
#define PCI_EXT_CAP_ID_VC 2
459
#define PCI_EXT_CAP_ID_DSN 3
460
#define PCI_EXT_CAP_ID_PWR 4
461
462
/* Extended Capability lists*/
463
#define PCIE_EXT_CAP_OFFSET 0x100
464
#define PCIE_EXT_CAP_AER_ID 0x0001
465
#define PCIE_EXT_CAP_L1SS_ID 0x001E
466
#define PCIE_EXT_CAP_LTR_ID 0x0018
467
#define PCIE_EXT_CAP_RESIZABLE_BAR 0x0015
468
469
/* Advanced Error Reporting */
470
#define PCI_ERR_UNCOR_STATUS 4
/* Uncorrectable Error Status */
471
#define PCI_ERR_UNC_TRAIN 0x00000001
/* Training */
472
#define PCI_ERR_UNC_DLP 0x00000010
/* Data Link Protocol */
473
#define PCI_ERR_UNC_POISON_TLP 0x00001000
/* Poisoned TLP */
474
#define PCI_ERR_UNC_FCP 0x00002000
/* Flow Control Protocol */
475
#define PCI_ERR_UNC_COMP_TIME 0x00004000
/* Completion Timeout */
476
#define PCI_ERR_UNC_COMP_ABORT 0x00008000
/* Completer Abort */
477
#define PCI_ERR_UNC_UNX_COMP 0x00010000
/* Unexpected Completion */
478
#define PCI_ERR_UNC_RX_OVER 0x00020000
/* Receiver Overflow */
479
#define PCI_ERR_UNC_MALF_TLP 0x00040000
/* Malformed TLP */
480
#define PCI_ERR_UNC_ECRC 0x00080000
/* ECRC Error Status */
481
#define PCI_ERR_UNC_UNSUP 0x00100000
/* Unsupported Request */
482
#define PCI_ERR_UNCOR_MASK 8
/* Uncorrectable Error Mask */
483
/* Same bits as above */
484
#define PCI_ERR_UNCOR_SEVER 12
/* Uncorrectable Error Severity */
485
/* Same bits as above */
486
#define PCI_ERR_COR_STATUS 16
/* Correctable Error Status */
487
#define PCI_ERR_COR_RCVR 0x00000001
/* Receiver Error Status */
488
#define PCI_ERR_COR_BAD_TLP 0x00000040
/* Bad TLP Status */
489
#define PCI_ERR_COR_BAD_DLLP 0x00000080
/* Bad DLLP Status */
490
#define PCI_ERR_COR_REP_ROLL 0x00000100
/* REPLAY_NUM Rollover */
491
#define PCI_ERR_COR_REP_TIMER 0x00001000
/* Replay Timer Timeout */
492
#define PCI_ERR_COR_MASK 20
/* Correctable Error Mask */
493
/* Same bits as above */
494
#define PCI_ERR_CAP 24
/* Advanced Error Capabilities */
495
#define PCI_ERR_CAP_FEP(x) ((x) & 31)
/* First Error Pointer */
496
#define PCI_ERR_CAP_ECRC_GENC 0x00000020
/* ECRC Generation Capable */
497
#define PCI_ERR_CAP_ECRC_GENE 0x00000040
/* ECRC Generation Enable */
498
#define PCI_ERR_CAP_ECRC_CHKC 0x00000080
/* ECRC Check Capable */
499
#define PCI_ERR_CAP_ECRC_CHKE 0x00000100
/* ECRC Check Enable */
500
#define PCI_ERR_HEADER_LOG 28
/* Header Log Register (16 bytes) */
501
#define PCI_ERR_ROOT_COMMAND 44
/* Root Error Command */
502
#define PCI_ERR_ROOT_STATUS 48
503
#define PCI_ERR_ROOT_COR_SRC 52
504
#define PCI_ERR_ROOT_SRC 54
505
506
/* Virtual Channel */
507
#define PCI_VC_PORT_REG1 4
508
#define PCI_VC_PORT_REG2 8
509
#define PCI_VC_PORT_CTRL 12
510
#define PCI_VC_PORT_STATUS 14
511
#define PCI_VC_RES_CAP 16
512
#define PCI_VC_RES_CTRL 20
513
#define PCI_VC_RES_STATUS 26
514
515
/* Power Budgeting */
516
#define PCI_PWR_DSR 4
/* Data Select Register */
517
#define PCI_PWR_DATA 8
/* Data Register */
518
#define PCI_PWR_DATA_BASE(x) ((x) & 0xff)
/* Base Power */
519
#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3)
/* Data Scale */
520
#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7)
/* PM Sub State */
521
#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3)
/* PM State */
522
#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7)
/* Type */
523
#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7)
/* Power Rail */
524
#define PCI_PWR_CAP 12
/* Capability */
525
#define PCI_PWR_CAP_BUDGET(x) ((x) & 1)
/* Included in system budget */
526
527
/* Latency Tolerance Reporting */
528
#define PCI_LTR_MAX_SNOOP 4
529
#define PCI_LTR_MAX_NOSNOOP 6
530
531
/* PCIe Resizable BARs */
532
#define PCI_REBAR_CAP_OFFSET 0x4
533
#define PCI_REBAR_CAP_SIZE_MASK 0xfffffff0
534
#define PCI_REBAR_CTRL_OFFSET 0x8
535
#define PCI_REBAR_CTRL_NBARS_MASK 0xe0
536
#define PCI_REBAR_CTRL_NBARS_SHIFT 5
537
#define PCI_REBAR_CTRL_IDX_MASK 0x07
538
#define PCI_REBAR_CTRL_SIZE_MASK 0xffff0000
539
#define PCI_REBAR_CTRL_SIZE_SHIFT 16
540
541
/*
542
* The PCI interface treats multi-function devices as independent
543
* devices. The slot/function address of each device is encoded
544
* in a single byte as follows:
545
*
546
* 7:3 = slot
547
* 2:0 = function
548
*/
549
#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
550
#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
551
#define PCI_FUNC(devfn) ((devfn) & 0x07)
552
553
/* Translation from PCI_DEV() to devicetree bus and path.pci.devfn. */
554
#define PCI_DEV2DEVFN(sdev) (((sdev)>>12) & 0xff)
555
#define PCI_DEV2SEGBUS(sdev) (((sdev)>>20) & 0xfff)
556
557
#endif
/* PCI_DEF_H */
src
include
device
pci_def.h
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